LH79524/LH79525 User’s Guide
Overview
Version 1.0
1-5
CLCD Clock
50.803 MHz
This clock controls the data rate for pixel transfers to an external LCD
panel. This clock can be separately enabled, disabled and prescaled.
Source can be divided by 2
n
(n
≤
8). This clock can be individually halted
for power savings.
Serial Interface
Clock (UART[2:0] )
20 MHz
These clocks control the data transfer rates over the three UART inter-
faces. These clocks are all separate and can be separately enabled
and disabled. Clock source can be selected from HCLK or CLK OSC.
Counter/Timer
Clocks
25.415 MHz
These clocks control the transition rates for the internal timers.
The source can be selected from HCLK or the External Timer input
(CTCLK). Each timer is either clocked by CTCLK or HCLK divided by
2
n
(0 < n
≤
8).
RTC Clock
32.768 kHz
This clock controls the transition rate for the internal real-time clock.
The source can be selected from the 1 Hz Clock, RTC OSC, CLK PLL,
or an External RTC Clock connected to the XTAL32IN pin.
Clock Output
(CLKOUT)
50.803 MHz
This output clock is available on pin CLKOUT for use with external
peripherals. Input source can be FCLK, HCLK, or CLK OSC.
Table 1-2. Clock Descriptions (Cont’d)
NAME
FREQUENCY
(MAX.)
DESCRIPTION
