Overview
LH79524/LH79525 User’s Guide
1-4
Version 1.0
1.3 Clock Strategy
The SoCs have two crystal oscillators. One oscillator, CLK OSC, is used to drive both PLLs
and the three UARTs, among others. This oscillator supports a frequency range from 10
to 20 MHz. The second oscillator, RTC CLK, is a 32.768 kHz oscillator, also requiring a
1.8 V source. This oscillator is used to generate a 1 Hz clock for the Real-time Clock.
The clock circuitry has two PLLs — one for the system clock generation and the other
for the USB clock generation. The output frequency of the PLLs ranges from 20 MHz to
304.819 MHz based on the PLL programmable dividers’ values.
The system clock frequency created in the Reset, Clock, and Power Controller (RCPC)
can be programmed to divide the PLL frequency by 1 or any even divisor between 2 and
30. The maximum ARM720T core operating frequency is 76.205 MHz and maximum sys-
tem operating frequency of 50.803 MHz. If UARTs 0, 1, or 2 are to be used, the system
clock frequency must not be set to less than 50% of the frequency applied to the crystal
input pin (XTALIN) for proper UART operation.
Table 1-2 is a list of the internal clocks with maximum frequency.
Table 1-2. Clock Descriptions
NAME
FREQUENCY
(MAX.)
DESCRIPTION
System Oscillator
Clock (CLK OSC)
20 MHz
External crystal oscillator input.
32.768 kHz
RTC OSC
32.768 kHz
External 32.768 kHz crystal oscillator input.
1 Hz Clock
1 Hz
The 1 Hz Clock is derived by dividing the RTC OSC by 32,768.
PLL System Clock
(CLK PLL)
304.819 MHz
This is the output from the System PLL. The input for this clock is
CLK OSC, the System Oscillator Clock. The minimum output frequency
is 5 MHz.
USB PLL Clock
(USB PLL)
304.819 MHz
This is the output from the USB PLL; the input is CLK OSC. It can be
programmed for any frequency between 5 MHz and 304.819 MHz.
AHB Fast CPU
Clock (FCLK)
76.205 MHz
This clock controls the CPU instruction execution speed. It is derived from
the CLK PLL clock, and is prescaled by 2, 4, ...30. The clock is halted
HIGH when the RCPC is in any power down mode other than Standby.
AHB Clock (HCLK)
50.803 MHz
This clock controls the AHB execution speed. It is derived from CLK
PLL and its frequency is CLK PLL divided by 2, 4, ...30. The clock is
halted HIGH when the RCPC is in any power down mode other than
Standby mode. It can be programmed for power savings to turn off
clock individually to DMAC, EMC, EMAC, USB, and CLCDC.
USB Clock
48.0 MHz
The USB Clock controls the 12 MHz full-speed USB Device interface.
Selectable input from HCLK or USB PLL. Frequency is required to be
48 MHz for proper USB operation (hardware divides by 4).
SSP Clock
50.803 MHz
This clock controls the SSP and the I
2
S interfaces. Source is either
HCLK or CLK OSC. Can be divided by 2
n
(n
≤
8). This clock can be
individually halted for power savings.
ADC Clock
50.803 MHz
Controls the Touch Screen Controller (TSC) and Brownout Detector. In-
put source choice of HCLK or CLK OSC. Source can be divided by 2
n
(n
≤
8). This clock can be individually halted for power savings.
