Samsung MSYS 5150, Руководство по обслуживанию

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S I G N A L PIN No. Type Description
EN85 65 I Enable 8085 bus mode
When EN85 is connected to ground, 8085 bus mode is selected and the
modem can interface directly to an 8085 compatible microprocessor bus
using READ and WRITE. When EN85 is pulled-up to +5V, 6500 bus
mode is selected and the modem can interface directly to a 6500
compatible micro-processor using
φ
2 and R/W.
X C L K O 70 O XCLKO output
This output pin is a 12 MHz (KS16116) or 19 MHz (KS16117) square wave
output derived from XTALI.
Y C L K O 71 O YCLKO output
This output pin is a 6 MHz (KS16116) or 9.5 MHz (KS16117) square wave
output derived from XTALI.
SEPXO 86 O Serial eye pattern bit data
SEPYO 90 These two outputs provide two serial bit streams containing eye pattern
display data for the oscilloscope X and Y axis. The data words are 9 bits
long with the sigh bit shifted out first and the bits clocked by the rising
edge of SEPCLK.
SEPCLKX 84 O Serial eye pattern bit clock
SEPCLK is a 230.4 KHz clock used to shift the eye pattern data into the
serial-to-parallel converters. SEPXO and SEPYO are shifted out by the
modem on the rising edge of SEPCLKX.
S E P W C L K 83 O Serial eye pattern word clock
SEPWCLK (9600Hz) provides SEPXO and SEPYO 9-bit word timing and
its rising edge is used for copying the output of the serial to parallel
converters into the X and Y digital-to-analog converters.
T X A O 44 O Transmitter analog output
The TXAO can supply a maximum of 2.5 .015 volts into a load
resistance of 10K
Ω
(minimum). An external analog smoothing filter with
transfer function 28735.63/(S+11547.34) is required.
RXAI 45 I Receiver analog input
The input impedance of RXAI is greater than 1M
Ω
. An external analog
anti-aliasing filter with transfer function 21551.72/(S+11547.34) is
required between the line interface and the modem RAXI input.
The maximum input signal level into the anti-aliasing filter should not
exceed 0 dBm.
Digital Loopback
SEPCLK 85 O Over-sampling Clock Output. 2.304MHz clock output. Normally tied to
ECLKIN1.
ECLKIN1 25 I Over-sampling Clock Input. Input to the AFE’s over-sampling clock
input pin. Normally connected to SEPCLK.
R C V O 98 O Disable Transmitter Output. “1” on this pin disables AFE’s transmitter.
Normally connected to RCVI.
S W G A I N O 99 O Externally connected to SWGAINI pin.
Table 2-1 Hardware Interface Signal Descriptions (Cont.)
Samsung Electronics 5-21
Circuit Description