Samsung MSYS 5150, Руководство по обслуживанию

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S I G N A L PIN No. Type Description
RS4 56 I Register select bus
RS3 57 These lines are used to address interface memory registers within the
RS2 58 modem. When CS is active, the modem decodes RS0 through RS4 to
RS1 59 address one of its 32 internal interface memory registers. RS4 is the most
RS0 60 significant bit. In a typical design, RS0-RS4 are connected to A0-A4
address lines of the host microprocessor.
D7 8 I/O Data bus
D6 9 These bi-directional data bus lines provide parallel data transfer between
D5 10 the modem and the host microprocessor. D7 is the most signification bit.
D4 11 The direction of the D0-D7 data bus is controlled by the READ-
φ
2 and
D3 12 WRITE-R/W signals. When not being written into or read from, D0-D7
D2 13 assume the high impedance state.
D1 14
D0 15
CS 54 I Chip select
The modem is selected and decodes RS0-RS4 when CS becomes active at
which time data transfer between the modem and the host can take
place over the parallel data bus. Typically, CS is driven by address
decode logic.
READ-
φ
2 55 I Read enable (bus mode) or phase2 (6500 bus mode)
If 8085 bus mode is selected (EN85 is connected to ground), this
signal acts as the READ input. If 6500 bus mode is selected (EN85
is pulled-up to +5V), this signal acts as the Phase 2 clock input.
WRITE-R/W 53 I W rite enable (bus mode) or R/W (6500 bus mode)
If 8085 bus mode is selected (EN85 is connected to ground), this
signal acts as the WRITE input. If 6500 bus mode is selected (EN85
is pulled-up to +5V), this signal acts as the R/W strobe.
IRQ 52 O Interrupt request
The modem can use IRQ to interrupt the host microprocessor program
execution.IRQ can be enabled in the modem interface memory to be
asserted in response to a specified change of conditions in the modem
status.IRQ is an open drain output and must be connected to an
external pull up resistor of suitable value (typically, a 5.6KW, 1/4 watt,
5% resistor is adequate).
TXDI 79 I Transmit data input
TXDI is the modem’s transmit data serial input. When configured for
serial data mode (PDME bit is reset) the modem accepts data bits for
transmission via this input. When transmitting data, the modem reads
the TXDI pin on the rising edge of DCLK. When the modem is
configured for parallel data mode (PDME bit is set), the TXID pin is
ignored and transmit data is accepted by the modem via the DBFR
register.
R X D O 95 O Receive data output
RXDO is the modem receive data output. Received data is output to the
DTE via the RXDO pin in both serial and parallel data modes (PDME bit
set or reset). When receiving data, the modem outputs a data bit on the
falling edge of DCLK. The center of RXDO bits coincides with the rising
edge of DCLK, thus, the DTE should read RXDO on the rising edge of
DCLK.
H A R D WARE INTERFACE SIGNALS DESCRIPTIONS
Table 2-1 Hardware Interface Signal Descriptions
Samsung Electronics 5-19
Circuit Description