Samsung MSYS 5150, Руководство по обслуживанию

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SIGNAL DESCRIPTIONS
Table 1-1 KS32C6100 Signal Descriptions
S I G N A L PIN No. Type Description
M C L K 206 I External master clock input. It has a 50% duty cycle and an operating
f requency up to 33MHz.
CLKSEL 201 I Clock select. When CLKSEL is “1” (High level), MCLK is used as
internal master clock directly. When CLKSEL is “0” (Low level),
the external MCLK frequency is divided by two and then used as
the internal master clock.
nRSTO 194 O Reset signal output from watch dog timer.
nRESET 195 I Not reset. nRESET is the global reset input for the KS32C6100.
To reset system, nRESET must be held to Low level
for at least 65 machine cycles.
n B K 0 H W 198 I Bank 0 data bus width select. When nB0HW is “0”,
the bank 0 data bus is recognized as 16-bit wide.
When nB0HW is “1”, the bank 0 data bus is recognized as 32-bit wide.
T M O D E 197 I Test pin. For normal operation, this pin should be connected to GND.
T C K 208 I TA P controller clock.
T M S 204 I TA P controller mode select.
TDI 202 I TA P controller data input.
T D O 203 O TA P controller data output.
TnRST 196 I TA P controller reset signal.
XA[23:0]/ 40~45 I/O The 24-bit address data bus, XA[23:0], acts as an output
ExtMA[23:0] 47~51 when the ARM core or DMA is accessing the chip-select banks and
54~60 covers the full 16M-word (32-bit) address range of each ROM and
63~68 SRAM bank, and 64K-byte external I/O address range; or it acts as an
input in external master mode and corresponds to ExtMA[23:0],
the lower 24 bits out of 28-bit external master address bus
ExtMA[27:0].
XD[31:0] 75~79 I/O External bi-directional three-state 32-bit data bus. The KS32C6100 data
81~87 bus supports external 8-bit, 16-bit, and 32-bit bus connection.
89~94
96~102
106~112
nRCS[3:0] 69 O Not ROM chip select. The KS32C6100 can access up to four external
72~74 ROM banks. nRCS0 corresponds to ROM bank 0, nRCS1 to bank 1,
and so on.
nSCS 28 O Not RSAM chip select. Selection to access external SRAM bank.
nECS[3:0] 29~32 O Not external chip select. Four I/O banks are provided for memory-
mapped external I/O operations, each of which contains up to 16K
bytes. The four nECS signals are used to select the four I/O banks
respectively.
n O E 37 O Not data output enable for ROM/SRAM/External IO.
Whenever a memory access for ROM/SRAM/External IO occurs,
the nOE output controls the output enable port of the specific device.
5-10 Samsung Electronics
Circuit Description