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PSI System Controls and Diagnostics
F3200E User Manual
F3200E_UM_180726 Page 68 of 107
15.2 F3200E Circuit Overview
The circuitry is arranged on a main board plus two daughter boards. The A60 is a standard
Pyramid processor card which handles the communications interfaces to the host computer. The
fiber optic mezzanine card mounts the six fiber optic devices.
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
FPGA
2
Cal 1
Cal 2
Cal 3
Cal 4
FPGA
1
NIOS
CPU
SRAM
Signal
inputs
DAC
Range select
DRAM
Flash
DAC
HV
module
HV output
ADC
Gate in
Gate out
Opto A in
Opto
Opto B in
Opto
+24 V switched out
Relay
+5 V switched out
Relay
Serial
drivers
Ethernet
RS-232 / RS-485
RX
TX
LEDs
Watchdog
Reset
DC-DC converters
24 V in
Fan
24 V out
+5 +3.3 +2.5 +1.5
+15 -15
Mode
Addr
NIOS
CPU
A60
DAC
DAC
Fiber
optic
mezz
RX
TX
TX
TX
+15 (HV)
HV input
ADC
Analog outputs
ADC
ADC
ADC
ADC
Analog inputs
JPRs
Digital outputs
Digital inputs
Port 1
Port 2
Figure 57. F3200E block schematic.
15.2.1 Signal input stages
Each signal processing channel comprises four distinct I-V converter circuits, differing in the
value of the feedback resistors. Stabilization capacitors in the feedback loops give an effective
time constant of 0.8 µsec on each range. One of the four circuits is switched in by analog gate
switches at any time in order to establish a particular full scale current. The input impedance is
determined by the “on” resistance of the analog gate, which is 40 ohms typical.
The I-V converter stage is followed by a four-pole low-pass filter with -3dB rolloff set to 250
kHz, to provide anti-aliasing for the analog to digital converter.