Omron 3G8F7-CRM21, Руководство пользователя

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64
PC Watchdog Timer
Section 5-5
[REQ_RES by interrupts]
Precautions for Correct Use
A program must be made to reset the Board no earlier than 1 second after a
Board reset request is received.
5-5 PC Watchdog Timer
The PC Watchdog Timer enables the Board communications to stop
automatically following the stop of the user application that controls the Board.
When the Timer is enabled, the communications stops automatically if the
user application does not update the Timer value for a certain time period. In
other word, you have to be sure the user application updates the Timer value
periodically so that the normal operation is notified to the Board.
[Enabling the PC Watchdog Timer]
Step Operation procedure Access to Shared Memory
1. Confirm the Interrupt
cause. Confirm the cause of REQ_RES interrupt in the Interrupt
Request Indication register (0x0005).
2. Clear the Interrupt cause. Set the REQ_RES flag of the Interrupt Clear register
(0x0006) to 1.
3. Wait for 1 second. Have a WAIT for 1 second.
4. Reset the Board. Write 1 in the Board Reset (0x0001) and reset the Board.
5. Process after the reset. Redo the steps in Section 5-2-2.
Step Operation procedure Access to Shared Memory
1. Set the command
SET_PC_WDT. Set the time-out value for CompoNet Master Board in the
Command area (PC
→
BD) (0x3200) to set the
command SET_PC_WDT.
2. Notify that the command
is set. Set the CMD flag of the Interrupt Trigger register (0x0002)
to 1.
3. Confirm that the
command set has been
notified. Confirm the CMD flag of the Interrupt Request
Confirmation register (0x0003) changes to 0.
4. Wait for a command
acknowledgment. Confirm the CMD_ACK flag of the Interrupt Request
Indication register (0x0005) changes to 1. (Confirm by an
interrupt or by polling.)
5. Read the command
response SET_PC_WDT. The command response SET_PC_WDT from CompoNet
Master Board is stored in Command area (BD
→
PC)
(0x3210). Read it.
6. Release the command
acknowledgment
interrupt. Set the CMD_ACK flag in Interrupt Clear register
(0x0006) to 1, to clear the interrupt cause.