NXP Semiconductors MPC5605BK, Справочное руководство

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Chapter 34 Error Correction Status Module (ECSM)
MPC5606BK Microcontroller Reference Manual, Rev. 2
934 Freescale Semiconductor
FRCNCI Force SRAM Continuous Non-correctable Data Inversions
The assertion of this bit forces the SRAM controller to create 2-bit data inversions, as defined by the
bit position specified in ERRBIT[6:0] and the overall odd parity bit, continuously on every write
operation.
After this bit has been enabled to generate another continuous non-correctable data inversion, it
must be cleared before being set again to properly re-enable the error generation logic.
The normal ECC generation takes place in the SRAM controller, but then the polarity of the bit
position defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error
in the SRAM.
0 No SRAM continuous 2-bit data inversions are generated.
1 2-bit data inversions in the SRAM are continuously generated.
FR1NCI Force SRAM One Non-correctable Data Inversions
The assertion of this bit forces the SRAM controller to create one 2-bit data inversion, as defined by
the bit position specified in ERRBIT[6:0] and the overall odd parity bit, on the first write operation
after this bit is set.
The normal ECC generation takes place in the SRAM controller, but then the polarity of the bit
position defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error
in the SRAM.
After this bit has been enabled to generate a single 2-bit error, it must be cleared before being set
again to properly re-enable the error generation logic.
0 No SRAM single 2-bit data inversions are generated.
1 One 2-bit data inversion in the SRAM is generated.
ERRBIT Error Bit Position
The vector defines the bit position that is complemented to create the data inversion on the write
operation. For the creation of 2-bit data inversions, the bit specified by this field plus the odd parity
bit of the ECC code are inverted.
The SRAM controller follows a vector bit ordering scheme where LSB = 0. Errors in the ECC
syndrome bits can be generated by setting this field to a value greater than the SRAM width. For
example, consider a 32-bit SRAM implementation.
The 32-bit ECC approach requires 7 code bits for a 32-bit word. For PRAM data width of 32 bits, the
actual SRAM (32b data + 7b for ECC) = 39 bits. The following association between the ERRBIT field
and the corrupted memory bit is defined:
if ERRBIT = 0, then SRAM[0] of the odd bank is inverted
if ERRBIT = 1, then SRAM[1] of the odd bank is inverted
...
if ERRBIT = 31, then SRAM[31] of the odd bank is inverted
if ERRBIT = 64, then ECC Parity[0] of the odd bank is inverted
if ERRBIT = 65, then ECC Parity[1] of the odd bank is inverted
...
if ERRBIT = 70, then ECC Parity[6] of the odd bank is inverted
For ERRBIT values of 32 to 63 and greater than 70, no bit position is inverted.
Table 34-9. EEGR field descriptions (continued)
Field Description