NXP Semiconductors MPC5605BK, Справочное руководство

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Chapter 26 Deserial Serial Peripheral Interface (DSPI)
MPC5606BK Microcontroller Reference Manual, Rev. 2
624 Freescale Semiconductor
26.6.3.5.1 Filling the RX FIFO
The RX FIFO is filled with the received SPI data from the shift register. While the RX FIFO is not full,
SPI frames from the shift register are transferred to the RX FIFO. Every time an SPI frame is transferred
to the RX FIFO the RX FIFO counter is incremented by one.
If the RX FIFO and shift register are full and a transfer is initiated, the RFOF bit in the DSPI x _SR is set
indicating an overflow condition. Depending on the state of the ROOE bit in the DSPI x _MCR, the data
from the transfer that generated the overflow is ignored or put in the shift register. If the ROOE bit is set,
the incoming data is put in the shift register. If the ROOE bit is cleared, the incoming data is ignored.
26.6.3.5.2 Draining the RX FIFO
Host software or the eDMA can remove (pop) entries from the RX FIFO by reading the DSPI x _POPR. A
read of the DSPI x _POPR decrements the RX FIFO counter by one. Attempts to pop data from an empty
RX FIFO are ignored, the RX FIFO counter remains unchanged. The data returned from reading an empty
RX FIFO is undetermined.
See Section 26.5.8, DSPI POP RX FIFO Register (DSPIx_POPR) for more information on DSPI x _POPR.
When the RX FIFO is not empty, the RX FIFO drain flag (RFDF) in the DSPI x _SR is set. The RFDF bit
is cleared when the RX_FIFO is empty and the eDMA controller indicates that a read from DSPI x _POPR
is complete; alternatively the RFDF bit can be cleared by the host writing a 1 to it.
26.6.4 DSPI baud rate and clock delay generation
The SCK_ x frequency and the delay values for serial transfer are generated by dividing the system clock
frequency by a prescaler and a scaler with the option of doubling the baud rate.
Figure 26-14 shows conceptually how the SCK signal is generated.
Figure 26-14. Communications clock prescalers and scalers
26.6.4.1 Baud rate generator
The baud rate is the frequency of the serial communication clock (SCK_ x ). The system clock is divided
by a baud rate prescaler (defined by DSPI x _CTAR[PBR]) and baud rate scaler (defined by
DSPI x _CTAR[BR]) to produce SCK_ x with the possibility of doubling the baud rate. The DBR, PBR, and
BR fields in the DSPI x _CTARs select the frequency of SCK_ x using the following formula:
Table 26-25 shows an example of a computed baud rate.
Prescaler
1
Scaler
1 + DBR
System Clock SCK_x
SCK baud rate
f
SYS
PBRPrescalerValue
----------------------------------------------------------
1 DBR +
BRScalerValue
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