NXP Semiconductors MPC5605BK, Справочное руководство

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Chapter 24 LIN Controller (LINFlexD)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 487
The access to the BDRM register is shown in Table 24-7 .
Table 24-8 lists some common scenarios, controller responses, and suggestions when the LINFlexD
controller is acting as a UART receiver.
Table 24-7. BDRM access in UART mode
Access Mode
1
1
As specified by UARTCR[RFBM]
Word length
2
2
As specified by the WL1 and WL0 bits of the UARTCR register
IPS operation result
Read Byte4 FIFO Byte OK
Read Byte5-6-7 FIFO Byte IPS transfer error
Read Half-word2-3 FIFO Byte IPS transfer error
Read Word FIFO Byte IPS transfer error
Read Byte4-5-6-7 FIFO Half-word IPS transfer error
Read Half-word2 FIFO Half-word OK
Read Half-word3 FIFO Half-word IPS transfer error
Read Word FIFO Half-word IPS transfer error
Write Byte4-5-6-7 FIFO Byte/Half-word IPS transfer error
Write Half-word2-3 FIFO Byte/Half-word IPS transfer error
Write Word FIFO Byte/Half-word IPS transfer error
Read Byte4-5-6-7 BUFFER Byte/Half-word OK
Read Half-word2-3 BUFFER Byte/Half-word OK
Read Word BUFFER Byte/Half-word OK
Write Byte4-5-6-7 BUFFER Byte/Half-word IPS transfer error
Write Half-word2-3 BUFFER Byte/Half-word IPS transfer error
Write Word BUFFER Byte/Half-word IPS transfer error
Table 24-8. UART receiver scenarios
Scenario Responses and suggestions
The software does not know (in advance) how many
bytes will be received. Do not program UARTCR[RDFLRFC] in advance. When
this field is zero (as it is after reset), reception occurs on
a byte-by-byte basis. Therefore, the state machine will
move to IDLE state after each byte is received.
UARTCR[RDFLRFC] is programmed for a certain
number of bytes received, but the actual number of bytes
received is smaller. The reception will hang. In this case, the software must
monitor the UARTSR[TO] field, and move to IDLE state
by setting LINCR1[SLEEP].