NXP Semiconductors MPC5605BK, Справочное руководство

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Chapter 26 Deserial Serial Peripheral Interface (DSPI)
MPC5606BK Microcontroller Reference Manual, Rev. 2
626 Freescale Semiconductor
Table 26-28 shows an example of the computed delay after transfer.
26.6.4.5 Peripheral chip select strobe enable (CS5_ x )
The CS5 _x signal provides a delay to allow the CS x signals to settle after transitioning thereby avoiding
glitches. When the DSPI is in master mode and PCSSE bit is set in the DSPI x _MCR, CS5 _x provides a
signal for an external demultiplexer to decode the CS4_ x signals into as many as 32 glitchfree CS x signals.
Figure 26-15 shows the timing of the CS5 _x signal relative to CS signals.
Figure 26-15. Peripheral chip select strobe timing
The delay between the assertion of the CS x signals and the assertion of CS5 _x is selected by the PCSSCK
field in the DSPI x _CTAR based on the following formula:
At the end of the transfer the delay between CS5 _x negation and CS x negation is selected by the PASC
field in the DSPI x _CTAR based on the following formula:
Table 26-29 shows an example of the computed t
PCSSCK
delay.
Table 26-30 shows an example of the computed the t
PASC
delay.
Table 26-28. Delay after transfer computation example
PDT Prescaler value DT Scaler value
f
SYS
Delay after transfer
0b01 3 0b1110 32768 64 MHz 1.54 ms
Table 26-29. Peripheral chip select strobe assert computation example
PCSSCK Prescaler
f
SYS
Delay before transfer
0b11 7 64 MHz 109.4 ns
t
DT
=
f
SYS
DT

PDT
1

CS5_ x
CSx
t
PCSSCK
t
PASC
t
PCSSCK
=
PCSSCK

f
SYS
1
t
PASC
=
PASC

f
SYS
1