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Chapter 30 Flash Memory
MPC5606BK Microcontroller Reference Manual, Rev. 2
818
Freescale Semiconductor
30.5.1.5
CFlash Low/Mid Address Space Block Select Register (CFLASH_LMS)
The CFLASH_LMS register provides a means to select blocks to be operated on during erase.
Offset: 0x00010
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MSL
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
0
0
LSL
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 30-10. CFlash Low/Mid address space block Select register (CFLASH_LMS)
Table 30-20. CFLASH_LMS field descriptions
Field
Description
MSL
Mid Address Space Block Select
A value of 1 in the select register signifies that the block is selected for erase.
A value of 0 in the select register signifies that the block is not selected for erase. The reset
value for the select register is 0, or not selected.
MSL[1:0] are related to sectors B0F7-6, respectively.
The blocks must be selected (or deselected) before doing an erase interlock write as part of
the erase sequence. The select register is not writable once an interlock write is completed
or if a high voltage operation is suspended.
In the event that blocks are not present (due to configuration or total memory size), the
corresponding MSL bits will default to not selected, and will not be writable. The reset value
will always be 0, and register writes will have no effect.
0 Mid address space block is not selected for erase.
1 Mid address space block is selected for erase.
LSL
Low Address Space Block Select
A value of 1 in the select register signifies that the block is selected for erase.
A value of 0 in the select register signifies that the block is not selected for erase. The reset
value for the select register is 0, or not selected.
LSL[5:0] are related to sectors B0F5-0, respectively. LSL[15:6] are not used for this memory
cut.
The blocks must be selected (or deselected) before doing an erase interlock write as part of
the erase sequence. The select register is not writable once an interlock write is completed
or if a high voltage operation is suspended.
In the event that blocks are not present (due to configuration or total memory size), the
corresponding LSL bits will default to not selected, and will not be writable. The reset value
will always be 0, and register writes will have no effect.
Bits LSL[15:6] are read-only and locked at 0.
0 Low address space block is not selected for erase.
1 Low address space block is selected for erase.
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