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ML51/ML54/ML56 

Sep. 01, 2020 

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Rev 2.00 

 

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hnical Reference 

Manual

 

 

 

Interrupt Service 

6.2.4.4

The  interrupt  flags  are  sampled  every  system  clock cycle. In  the  same  cycle, the  sampled  interrupts 
are polled and their priority is resolved. If certain conditions are met then the hardware will execute an 
internally generated LCALL instruction, which will vector the process to the appropriate interrupt vector 
address. The conditions for generating the LCALL are, 

1. An interrupt of equal or higher priority is not currently being serviced. 

2. The current polling cycle is the last cycle of the instruction currently being executed. 

3. The current instruction does not involve a  write to any  enabling or priority setting  bits and  is not  a 
RETI. 

If  any  of  these  conditions  are  not  met,  then  the  LCALL  will  not  be  generated.  The  polling  cycle  is 
repeated every system clock cycle. If an interrupt flag is active in one cycle but not responded to for 
the above conditions are not met, if the flag is not still active when the blocking condition is removed, 
the denied interrupt will not be serviced. This means that the interrupt flag, which was once active but 
not serviced is not remembered. Every polling cycle is new. 

The  processor  responds  to  a  valid  interrupt  by  executing  an  LCALL  instruction  to  the  appropriate 
service  routine.  This  action  may  or  may  not  clear  the  flag,  which  caused  the  interrupt  according  to 
different interrupt source. The hardware LCALL behaves exactly like the software LCALL instruction. 
This  instruction  saves  the  Program  Counter  contents  onto  the  Stack  RAM  but  does  not  save  the 
Program  Status  Word  (PSW).  The  PC  is  reloaded  with  the  vector  address  of  that  interrupt,  which 
caused  the  LCALL.  Execution  continues  from  the  vectored  address  until  an  RETI  instruction  is 
executed. On execution of the RETI instruction, the processor pops the Stack and loads the PC with 
the contents at the top of the stack. User should take care that the status of the stack. The processor 
does  not  notice  anything  if  the  stack  contents  are  modified  and  will  proceed  with  execution  from  the 
address put back into PC. Note that a simple RET instruction would perform exactly the same process 
as a RETI instruction, but it would not inform the Interrupt controller that the interrupt service routine is 
completed. RET  would  leave  the  controller  still  thinking  that  the  service  routine  is  underway,  making 
future interrupts impossible. 

 

Interrupt Latency 

6.2.4.5

The  response  time  for  each  interrupt  source  depends  on  several  factors,  such  as  the  nature  of  the 
interrupt  and  the  instruction  underway.  Each  interrupt  flags  are  polled  and  priority  decoded  each 
system clock cycle. If a request is active and all three previous conditions are met, then the hardware 
generated LCALL is executed. This LCALL itself takes 4 clock cycles to be completed. Thus, there is a 
minimum reaction time of 5 clock cycles between the interrupt flag being set and the interrupt service 
routine being executed. 

A longer response time should be anticipated if any of the three conditions are not met. If a higher or 
equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the 
service routine currently being executed. If the polling cycle is not the last clock cycle of the instruction 
being  executed,  then  an  additional  delay  is  introduced.  The  maximum  response  time  (if  no  other 
interrupt  is  currently  being  serviced  or  the  new  interrupt  is  of  greater  priority)  occurs  if  the  device  is 
performing a RETI, and then executes a longest 6-clock-cycle instruction as the next instruction. From 
the  time  an  interrupt  source  is  activated  (not  detected),  the  longest  reaction  time  is  16  clock  cycles. 
This  period  includes  5  clock  cycles  to  complete  RETI,  6  clock  cycles  to  complete  the  longest 
instruction, 1 clock cycle to detect the interrupt, and 4 clock cycles to complete the hardware LCALL to 
the interrupt vector location. 

Thus in a single-interrupt system the interrupt response time will always be more than 5 clock cycles 
and not more than 16 clock cycles. 

Содержание NuMicro ML51 Series

Страница 1: ...document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton Nuvoton is providing this document only for reference purp...

Страница 2: ...2 4 2 1 ML51 ML54 ML56 Series Pin Mapping 72 4 2 2 ML51 ML54 ML56 Series Pin Functional Description 74 5 BLOCK DIAGRAM 79 5 1 ML51 ML54 ML56 Series Full Function Block 79 6 FUNCTIONAL DESCRIPTION 80 6...

Страница 3: ...ake up Timer WKT 421 6 7 1 Overview 421 6 7 2 Block Diagram 421 6 7 3 Control Register 422 6 8 Pulse Width Modulated PWM 428 6 8 1 Overview 428 6 8 2 Features 428 6 8 3 Block Diagram 429 6 8 4 Functio...

Страница 4: ...13 4Register Description 566 6 14 Voltage Reference VREF 583 6 15 Analog Comparator Controller ACMP 585 6 15 1Overview 585 6 15 2Feature 585 6 15 3Block Diagram 586 6 15 4Functional Description 587 6...

Страница 5: ...7 APPLICATION CIRCUIT 702 7 1 Power Supply Scheme 702 7 2 Peripheral Application Scheme 703 8 ELECTRICAL CHARACTERISTICS 704 9 PACKAGE DIMENSIONS 705 9 1 LQFP 64L pin 7 0 x 7 0 x 1 4 mm 705 9 2 LQFP...

Страница 6: ...1AE Multi Function Pin assignment 38 Figure 4 1 18 ML51LD1AE Multi Function Pin assignment 41 Figure 4 1 19 ML54LD1AE Multi Function Pin assignment 44 Figure 4 1 20 ML56LD1AE Multi Function Pin assign...

Страница 7: ...6 5 4 Timer Counter 0 in Mode 3 391 Figure 6 5 5 Timer 2 Block Diagram 401 Figure 6 5 6 Timer 2 Auto Reload Mode and Input Capture Module Functional Block Diagram 402 Figure 6 5 7 Timer 2 Compare Mode...

Страница 8: ...Figure 6 12 2 I 2 C Bus Protocol 537 Figure 6 12 3 START Repeated START and STOP Conditions 537 Figure 6 12 4 Master Transmits Data to Slave by 7 bit 538 Figure 6 12 5 Master Reads Data from Slave by...

Страница 9: ...Figure 6 17 5 Example of Type A and Type B 8 COM and SEG Driving Signals of 1 4 Bias 615 Figure 6 18 1 RTC Block Diagram 635 Figure 6 19 1Touch Key block diagram 668 Figure 6 19 2 Touch Key Sensing M...

Страница 10: ...mer out Interval Under Different Pre scalars 414 Table 6 9 1 Serial Port 0 Mode baud rate Description 479 Table 6 9 2 Serial Port 1 Mode baud rate Description 480 Table 6 10 1 SC Activation and Cold R...

Страница 11: ...sets of 2 channels PWM output channels with 3 individual configurable period two analog comparators eight channel shared pin interrupt for all I O ports one 12 bit ADC at 500 ksps one RTC offers prog...

Страница 12: ...UID 128 bit Unique Customer ID UCID 128 bytes security protection memory SPROM Memories Flash Up to 64 KBytes of APROM for User Code 4 3 2 1 Kbytes of Flash for loader LDROM configure from APROM for I...

Страница 13: ...auto reload Timer 3 which can be the baud rate clock source of UARTs Watchdog 6 bit free running up counter for WDT time out interval Selectable time out interval is 1 66 ms 3413 12 ms since WDT_CLK 3...

Страница 14: ...Tick and Alarm Match interrupt Supports chip wake up from Idle or Power down mode while a RTC interrupt signal is generated Support clock source selectable from LXT or LIRC Analog Interfaces Analog to...

Страница 15: ...er sequence Slave mode up to 12 Mhz ISO 7816 3 Two sets ISO 7816 3 device Supports ISO 7816 3 compliant T 0 T 1 Supports full duplex UART mode GPIO Four I O modes Quasi bidirectional mode Push Pull Ou...

Страница 16: ...mable sensitivity levels for each channel Programmable scanning speed for different applications Supports effect when in Power down mode Supports single key scan and programmable periodic key scan Pro...

Страница 17: ...eries Package Type Package ML51 ML54 ML56 ML51xB ML51xC ML51xD ML54xD ML56xD MSOP10 ML51BB9AE TSSOP14 ML51DB9AE TSSOP20 ML51FB9AE SOP20 ML51OB9AE QFN20 3x3 ML51XB9AE TSSOP28 ML51EB9AE ML51EC0AE SOP28...

Страница 18: ...128 128 128 128 System Frequency MHz 24 24 24 24 24 24 24 24 GPIO 7 11 16 16 17 24 24 28 16 bit Timer 4 4 4 4 4 4 4 4 PWM 5 6 6 6 6 6 6 6 Analog Comparator 2 2 Internal Voltage Reference Y Y PDMA 2 2...

Страница 19: ...MHz 24 24 24 24 24 24 GPIO 24 24 28 28 28 43 16 bit Timer 4 4 4 4 4 4 PWM 6 6 6 6 6 6 Analog Comparator 2 2 2 2 2 2 Internal Voltage Reference Y Y Y Y Y Y PDMA 2 2 2 2 2 2 RTC LCD Connectivity ISO 781...

Страница 20: ...System Frequency MHz 24 24 24 GPIO 28 43 56 16 bit Timer 4 4 4 PWM 6 2 2 2 6 2 2 2 6 2 2 2 Analog Comparator 2 2 2 Internal Voltage Reference Y Y Y PDMA 4 4 4 RTC Y Y Y LCD Connectivity ISO 7816 3 2 2...

Страница 21: ...stem Frequency MHz 24 24 24 GPIO 38 42 55 16 bit Timer 4 4 4 PWM 6 2 2 2 6 2 2 2 6 2 2 2 Analog Comparator 2 2 2 Internal Voltage Reference Y Y Y PDMA 4 4 4 RTC Y Y Y LCD 8x17 8x18 8x28 6x19 6x20 6x30...

Страница 22: ...4 4 PWM 6 2 2 2 6 2 2 2 6 2 2 2 Analog Comparator 2 2 2 Internal Voltage Reference Y Y Y PDMA 4 4 4 RTC Y Y Y LCD 8x17 8x18 8x28 6x19 6x20 6x30 4x21 4x22 4x32 Touch Key 6 9 14 Connectivity ISO 7816 3...

Страница 23: ...E Core Line Package Flash SRAM Reserve Temperature 1T 8051 Low power 51 Base 54 LCD 56 Touch B MSOP10 3x3 mm D TSSOP14 4 4x5 0 mm E TSSOP28 4 4x9 7 mm F TSSOP20 4 4x6 5 mm L LQFP48 7x7 mm M LQFP44 10x...

Страница 24: ...LQFP64 Package 4 1 1 1 Corresponding Part Number ML51SD1AE ML54SD1AE ML56SD1AE ML51SD1AE LQFP64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 48 47 46 45 44 43...

Страница 25: ...48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 P2 6 P2 5 P2 4 P2 3 P2 2 P2 1 P2 0 P1 3 P1 2 P1 1 P1 0 VLCD P5 7 P5 5 P5 4 P5 3 nRESET P5 6 P0 0 P0 1 P...

Страница 26: ...0 5 P0 6 P0 7 P5 2 P5 3 P1 7 P1 6 P1 5 P1 4 P4 0 P4 1 P4 2 P4 3 P4 4 P4 5 P5 1 P5 0 VSS P4 6 VDD P4 7 P3 3 P3 2 P3 1 P3 0 VREF AVSS P2 7 P2 6 Figure 4 1 3 ML51LD1AE Pin Assignment ML54LD1AE ML56LD1AE...

Страница 27: ...0 1 P0 2 P0 3 P0 6 P0 7 P5 2 P5 3 P5 4 P1 7 P1 6 P1 5 P1 4 P4 0 P4 1 P4 2 P4 3 P4 4 P4 5 P5 1 VSS P4 6 VDD P3 3 P3 2 P3 1 P3 0 VREF AVSS P2 7 P2 6 Figure 4 1 5 ML54MD1AE ML56MD1AE Pin Assignment QFN33...

Страница 28: ...3 P2 2 P2 1 P2 0 P5 5 P5 4 nRESET P5 6 P0 0 P0 1 P0 2 P0 3 P5 2 P5 3 P1 7 P1 6 P1 5 P1 4 P4 0 P4 1 P5 1 P5 0 LQFP32 Figure 4 1 7 ML51PC0AE ML51PB9AE Pin Assignment TSSOP28 Package 4 1 1 6 Correspondi...

Страница 29: ...24 23 22 21 20 19 18 17 16 15 P1 4 P1 5 P1 6 P1 7 VSS P4 6 VDD P3 2 P3 1 P3 0 VREF P2 5 P2 4 P2 3 P4 0 P4 1 P5 1 P5 0 nRESET P0 0 P0 1 P0 2 P0 3 P5 2 P5 3 P2 0 P2 1 P2 2 Figure 4 1 9 ML51UC0AE ML51UB...

Страница 30: ...13 12 11 VSS P4 6 VDD P3 2 P3 1 P3 0 VREF P2 5 P2 4 P2 3 P5 1 P5 0 nRESET P0 0 P0 1 P0 2 P0 3 P5 2 P5 3 P2 2 Figure 4 1 11 ML51OB9AE Pin Assignment QFN20 Package 4 1 1 10 Corresponding Part Number ML5...

Страница 31: ...esponding Part Number ML51DB9AE ML51DB9AE 2 1 4 3 6 5 7 12 13 10 11 8 9 14 TSSOP14 VSS P4 6 VDD P3 1 P3 0 P2 5 P2 4 P5 1 P5 0 nRESET P0 2 P0 3 P5 2 P5 3 Figure 4 1 13 ML51DB9AE Pin Assignment MSOP10 P...

Страница 32: ...T1_RXD I2C1_SDA PWM0_CH3 P0 3 SPI0_SS SPI1_SS UART1_TXD I2C1_SCL STADC PWM0_CH2 CLKO P0 4 UART0_RXD I2C0_SDA PWM0_CH1 P0 5 UART0_TXD I2C0_SCL PWM0_CH0 P3 6 PWM0_CH5 INT1 VDD VSS P0 6 UART0_RXD I2C1_SD...

Страница 33: ...4 UART2_TXD PWM0_CH1 X32_OUT 16 P5 3 UART0_TXD I2C0_SCL XT1_IN 17 P5 2 UART0_RXD I2C0_SDA XT1_OUT 18 P3 5 PWM2_CH0 T0 19 P3 4 PWM2_CH1 T1 20 P0 7 UART0_TXD I2C1_SCL PWM3_CH0 INT1 21 P0 6 UART0_RXD I2C...

Страница 34: ...44 P6 0 SPI0_MOSI 45 P1 4 I2C1_SCL 46 P1 5 I2C1_SDA 47 P1 6 UART0_TXD 48 P1 7 UART0_RXD 49 VSS 50 P4 6 PWM0_CH0 T0 CLKO INT0 51 VDD 52 P4 7 T1 53 P3 3 SPI1_SS PWM1_CH0 IC0 PWM0_BRAKE 54 P3 2 ADC_CH7 A...

Страница 35: ...D_SEG1 UART0_TXD I2C1_SCL PWM3_CH0 INT1 P3 4 LCD_SEG2 PWM2_CH1 T1 P3 5 LCD_SEG3 PWM2_CH0 T0 P5 2 UART0_RXD I2C0_SDA XT1_OUT P1 7 LCD_SEG18 UART0_RXD LCD_COM7 P1 6 LCD_SEG19 UART0_TXD LCD_COM6 P1 5 LCD...

Страница 36: ...CH1 X32_OUT 16 P5 3 UART0_TXD I2C0_SCL XT1_IN 17 P5 2 UART0_RXD I2C0_SDA XT1_OUT 18 P3 5 LCD_SEG3 PWM2_CH0 T0 19 P3 4 LCD_SEG2 PWM2_CH1 T1 20 P0 7 LCD_SEG1 UART0_TXD I2C1_SCL PWM3_CH0 INT1 21 P0 6 LCD...

Страница 37: ..._SEG22 SPI0_MOSI 45 P1 4 LCD_SEG21 I2C1_SCL LCD_COM4 46 P1 5 LCD_SEG20 I2C1_SDA LCD_COM5 47 P1 6 LCD_SEG19 UART0_TXD LCD_COM6 48 P1 7 LCD_SEG18 UART0_RXD LCD_COM7 49 VSS 50 P4 6 LCD_SEG17 PWM0_CH0 T0...

Страница 38: ...T0_RXD I2C0_SDA XT1_OUT P1 7 LCD_SEG18 UART0_RXD LCD_COM7 P1 6 LCD_SEG19 UART0_TXD LCD_COM6 P1 5 LCD_SEG20 I2C1_SDA LCD_COM5 P1 4 LCD_SEG21 I2C1_SCL LCD_COM4 P6 0 LCD_SEG22 SPI0_MOSI TK11 P6 1 LCD_SEG...

Страница 39: ...G0 UART0_RXD I2C1_SDA PWM3_CH1 INT0 22 VSS 23 VDD 24 P3 6 TK7 PWM0_CH5 INT1 25 P0 5 UART0_TXD I2C0_SCL TK6 PWM0_CH0 26 P0 4 UART0_RXD I2C0_SDA TK5 PWM0_CH1 27 P0 3 SPI0_SS SPI1_SS UART1_TXD I2C1_SCL T...

Страница 40: ...ART0_RXD LCD_COM7 49 VSS 50 P4 6 LCD_SEG17 PWM0_CH0 T0 CLKO INT0 51 VDD 52 P4 7 LCD_SEG16 LCD_COM0 T1 53 P3 3 LCD_SEG15 SPI1_SS LCD_COM1 PWM1_CH0 IC0 PWM0_BRAKE 54 P3 2 ADC_CH7 ACMP1_N1 LCD_SEG14 SPI1...

Страница 41: ...RXD I2C1_SDA PWM0_CH3 P0 3 SPI0_SS SPI1_SS UART1_TXD I2C1_SCL STADC PWM0_CH2 CLKO P0 4 UART0_RXD I2C0_SDA PWM0_CH1 P0 5 UART0_TXD I2C0_SCL PWM0_CH0 P0 6 UART0_RXD I2C1_SDA PWM3_CH1 INT0 P0 7 UART0_TXD...

Страница 42: ...1 16 P0 6 UART0_RXD I2C1_SDA PWM3_CH1 INT0 17 P0 5 UART0_TXD I2C0_SCL PWM0_CH0 18 P0 4 UART0_RXD I2C0_SDA PWM0_CH1 19 P0 3 SPI0_SS SPI1_SS UART1_TXD I2C1_SCL STADC PWM0_CH2 CLKO 20 P0 2 SPI0_CLK SPI1_...

Страница 43: ...7 VSS 38 P4 6 PWM0_CH0 T0 CLKO INT0 39 VDD 40 P4 7 T1 41 P3 3 SPI1_SS PWM1_CH0 IC0 PWM0_BRAKE 42 P3 2 ADC_CH7 ACMP1_N1 SPI1_CLK UART3_RXD PWM1_CH1 IC1 CLKO 43 P3 1 ADC_CH6 ACMP0_P3 ACMP1_P3 SPI1_MISO...

Страница 44: ...0_RXD I2C1_SDA PWM3_CH1 INT0 P0 7 LCD_SEG1 UART0_TXD I2C1_SCL PWM3_CH0 INT1 P5 2 UART0_RXD I2C0_SDA XT1_OUT P5 3 UART0_TXD I2C0_SCL XT1_IN P1 7 LCD_SEG18 UART0_RXD LCD_COM7 P1 6 LCD_SEG19 UART0_TXD LC...

Страница 45: ...CH0 INT1 16 P0 6 LCD_SEG0 UART0_RXD I2C1_SDA PWM3_CH1 INT0 17 P0 5 UART0_TXD I2C0_SCL PWM0_CH0 18 P0 4 UART0_RXD I2C0_SDA PWM0_CH1 19 P0 3 SPI0_SS SPI1_SS UART1_TXD I2C1_SCL STADC PWM0_CH2 CLKO 20 P0...

Страница 46: ...CLKO INT0 39 VDD 40 P4 7 LCD_SEG16 LCD_COM0 T1 41 P3 3 LCD_SEG15 SPI1_SS LCD_COM1 PWM1_CH0 IC0 PWM0_BRAKE 42 P3 2 ADC_CH7 ACMP1_N1 LCD_SEG14 SPI1_CLK UART3_RXD PWM1_CH1 IC1 CLKO 43 P3 1 ADC_CH6 ACMP0_...

Страница 47: ...XD I2C1_SCL PWM3_CH0 INT1 P5 2 UART0_RXD I2C0_SDA XT1_OUT P5 3 UART0_TXD I2C0_SCL XT1_IN P1 7 LCD_SEG18 UART0_RXD LCD_COM7 P1 6 LCD_SEG19 UART0_TXD LCD_COM6 P1 5 LCD_SEG20 I2C1_SDA LCD_COM5 P1 4 LCD_S...

Страница 48: ...L TK4 STADC PWM0_CH2 CLKO 20 P0 2 SPI0_CLK SPI1_CLK UART1_RXD I2C1_SDA TK3 PWM0_CH3 21 P0 1 SPI0_MISO SPI1_MISO UART2_RXD UART0_TXD TK2 PWM0_CH4 22 P0 0 SPI0_MOSI SPI1_MOSI UART2_TXD UART0_RXD TK1 PWM...

Страница 49: ...LCD_COM0 T1 41 P3 3 LCD_SEG15 SPI1_SS LCD_COM1 PWM1_CH0 IC0 PWM0_BRAKE 42 P3 2 ADC_CH7 ACMP1_N1 LCD_SEG14 SPI1_CLK UART3_RXD PWM1_CH1 IC1 CLKO 43 P3 1 ADC_CH6 ACMP0_P3 ACMP1_P3 LCD_SEG13 SPI1_MISO UA...

Страница 50: ...3_CH1 INT0 P0 7 LCD_SEG1 UART0_TXD I2C1_SCL PWM3_CH0 INT1 P5 2 UART0_RXD I2C0_SDA XT1_OUT P5 3 UART0_TXD I2C0_SCL XT1_IN P5 4 UART2_TXD PWM0_CH1 X32_OUT P1 7 LCD_SEG18 UART0_RXD LCD_COM7 P1 6 LCD_SEG1...

Страница 51: ...C1_SCL PWM3_CH0 INT1 16 P0 6 LCD_SEG0 UART0_RXD I2C1_SDA PWM3_CH1 INT0 17 P0 3 SPI0_SS SPI1_SS UART1_TXD I2C1_SCL STADC PWM0_CH2 CLKO 18 P0 2 SPI0_CLK SPI1_CLK UART1_RXD I2C1_SDA PWM0_CH3 19 P0 1 SPI0...

Страница 52: ...LCD_SEG15 SPI1_SS LCD_COM1 PWM1_CH0 IC0 PWM0_BRAKE 38 P3 2 ADC_CH7 ACMP1_N1 LCD_SEG14 SPI1_CLK UART3_RXD PWM1_CH1 IC1 CLKO 39 P3 1 ADC_CH6 ACMP0_P3 ACMP1_P3 LCD_SEG13 SPI1_MISO UART3_TXD UART0_TXD PWM...

Страница 53: ...UART0_RXD I2C0_SDA XT1_OUT P5 3 UART0_TXD I2C0_SCL XT1_IN P5 4 UART2_TXD PWM0_CH1 X32_OUT P1 7 LCD_SEG18 UART0_RXD LCD_COM7 P1 6 LCD_SEG19 UART0_TXD LCD_COM6 P1 5 LCD_SEG20 I2C1_SDA LCD_COM5 P1 4 LCD_...

Страница 54: ...PWM0_CH4 20 P0 0 SPI0_MOSI SPI1_MOSI UART2_TXD UART0_RXD TK1 PWM0_CH5 21 nRESET 22 P5 0 UART1_TXD I2C1_SCL UART0_TXD ICE_DAT 23 P5 1 UART1_RXD I2C1_SDA UART0_RXD ICE_CLK 24 P4 5 LCD_SEG31 LCD_COM4 UAR...

Страница 55: ...ECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual Pin ML56MD1AE Pin Function 40 P3 0 ADC_CH10 LCD_SEG12 SPI1_MOSI UART0_RXD PWM2_CH1 IC0 41 VREF 42 AVSS 43 P2 7 ADC_CH15 LCD_S...

Страница 56: ...UT PWM0_CH1 UART2_TXD P5 4 nRESET P5 6 PWM0_BRAKE PWM0_CH1 CLKO P0 0 SPI0_MOSI SPI1_MOSI UART2_TXD UART0_RXD PWM0_CH5 P0 1 SPI0_MISO SPI1_MISO UART2_RXD UART0_TXD PWM0_CH4 P0 2 SPI0_CLK SPI1_CLK UART1...

Страница 57: ...5 15 P5 6 TK0 PWM0_BRAKE PWM0_CH1 CLKO 16 nRESET 17 P5 0 UART1_TXD I2C1_SCL UART0_TXD ICE_DAT 18 P5 1 UART1_RXD I2C1_SDA UART0_RXD ICE_CLK 19 P4 1 LCD_SEG27 LCD_COM2 UART2_TXD I2C0_SCL PWM3_CH0 ACMP0_...

Страница 58: ...IN PWM0_CH0 UART2_RXD P5 5 X32_OUT PWM0_CH1 UART2_TXD P5 4 nRESET P5 6 PWM0_BRAKE PWM0_CH1 CLKO P0 0 SPI0_MOSI SPI1_MOSI UART0_RXD PWM0_CH5 P0 1 SPI0_MISO SPI1_MISO UART0_TXD PWM0_CH4 P0 2 SPI0_CLK SP...

Страница 59: ...12 P0 2 SPI0_CLK SPI1_CLK UART1_RXD I2C1_SDA PWM0_CH3 13 P0 1 SPI0_MISO SPI1_MISO UART0_TXD PWM0_CH4 14 P0 0 SPI0_MOSI SPI1_MOSI UART0_RXD PWM0_CH5 15 P5 6 PWM0_BRAKE PWM0_CH1 CLKO 16 nRESET 17 P5 0 U...

Страница 60: ...WM0_CH5 P0 1 SPI0_MISO SPI1_MISO UART0_TXD PWM0_CH4 P0 2 SPI0_CLK SPI1_CLK UART1_RXD I2C1_SDA PWM0_CH3 P0 3 SPI0_SS SPI1_SS UART1_TXD I2C1_SCL STADC PWM0_CH2 P5 2 UART0_RXD I2C0_SDA XT1_OUT P5 3 UART0...

Страница 61: ...UART1_TXD I2C1_SCL STADC PWM0_CH2 12 P0 2 SPI0_CLK SPI1_CLK UART1_RXD I2C1_SDA PWM0_CH3 13 P0 1 SPI0_MISO SPI1_MISO UART0_TXD PWM0_CH4 14 P0 0 SPI0_MOSI SPI1_MOSI UART0_RXD PWM0_CH5 15 P5 6 PWM0_BRAKE...

Страница 62: ...2C1_SCL STADC PWM0_CH2 P5 2 UART0_RXD I2C0_SDA XT1_OUT P5 3 UART0_TXD I2C0_SCL XT1_IN P2 0 ADC_CH5 ACMP0_N1 UART2_RXD I2C1_SDA PWM0_CH5 PWM0_BRAKE P2 1 ADC_CH4 ACMP0_P2 ACMP1_P2 UART2_TXD I2C1_SCL PWM...

Страница 63: ...ical Reference Manual Pin ML51EC0AE ML51EB9AE Pin Function 22 P0 1 SPI0_MISO SPI1_MISO UART0_TXD PWM0_CH4 23 P0 0 SPI0_MOSI SPI1_MOSI UART0_RXD PWM0_CH5 24 nRESET 25 P5 0 UART1_TXD I2C1_SCL UART0_TXD...

Страница 64: ..._SS UART1_TXD I2C1_SCL STADC PWM0_CH2 P5 2 UART0_RXD I2C0_SDA XT1_OUT P5 3 UART0_TXD I2C0_SCL XT1_IN P2 0 ADC_CH5 ACMP0_N1 UART2_RXD I2C1_SDA PWM0_CH5 PWM0_BRAKE P2 1 ADC_CH4 ACMP0_P2 ACMP1_P2 UART2_T...

Страница 65: ...L51UC0AE ML51UB9AE Pin Function 21 P0 2 SPI0_CLK SPI1_CLK UART1_RXD I2C1_SDA PWM0_CH3 22 P0 1 SPI0_MISO SPI1_MISO UART0_TXD PWM0_CH4 23 P0 0 SPI0_MOSI SPI1_MOSI UART0_RXD PWM0_CH5 24 nRESET 25 P5 0 UA...

Страница 66: ...ART1_TXD I2C1_SCL STADC PWM0_CH2 P5 2 UART0_RXD I2C0_SDA XT1_OUT P5 3 UART0_TXD I2C0_SCL XT1_IN P2 2 ADC_CH3 I2C1_SDA UART1_RXD PWM0_CH3 Figure 4 1 28 ML51FB9AE Multi Function Pin Assignment Pin ML51F...

Страница 67: ...PWM0_CH3 P0 3 SPI1_SS UART1_TXD I2C1_SCL STADC PWM0_CH2 P5 2 UART0_RXD I2C0_SDA XT1_OUT P5 3 UART0_TXD I2C0_SCL XT1_IN P2 2 ADC_CH3 I2C1_SDA UART1_RXD PWM0_CH3 Figure 4 1 29 ML51OB9AE Multi Function P...

Страница 68: ..._RXD PWM0_CH5 P0 1 SPI1_MISO UART0_TXD PWM0_CH4 P0 2 SPI1_CLK UART1_RXD I2C1_SDA PWM0_CH3 P0 3 SPI1_SS UART1_TXD I2C1_SCL STADC PWM0_CH2 P1 7 UART0_RXD P4 0 UART2_RXD I2C0_SDA ACMP1_O INT1 P4 1 UART2_...

Страница 69: ...nction 9 P0 0 SPI1_MOSI UART0_RXD PWM0_CH5 10 nRESET 11 P5 0 UART1_TXD I2C1_SCL UART0_TXD ICE_DAT 12 P5 1 UART1_RXD I2C1_SDA UART0_RXD ICE_CLK 13 P4 1 UART2_TXD I2C0_SCL ACMP0_O 14 P4 0 UART2_RXD I2C0...

Страница 70: ...UART1_RXD I2C1_SDA PWM0_CH3 P0 3 SPI1_SS UART1_TXD I2C1_SCL STADC PWM0_CH2 P5 2 UART0_RXD I2C0_SDA XT1_OUT P5 3 UART0_TXD I2C0_SCL XT1_IN Figure 4 1 31 ML51DB9AE Multi Function Pin Assignment Pin ML51...

Страница 71: ...P5 0 UART1_TXD I2C1_SCL UART0_TXD ICE_DAT nRESET P0 0 SPI1_MOSI UART0_RXD PWM0_CH5 P0 1 SPI1_MISO UART0_TXD PWM0_CH4 P2 0 ADC_CH5 UART2_RXD I2C1_SDA PWM0_CH5 PWM0_BRAKE Figure 4 1 32 ML51BB9AE Pin Ass...

Страница 72: ...5 6 5 5 16 5 P2 0 7 6 6 7 6 6 17 6 P1 3 8 7 7 8 7 P1 2 9 8 8 9 8 P1 1 10 9 9 10 9 P1 0 11 11 10 VLCD 12 10 10 P3 7 12 P5 7 13 13 P5 5 14 11 11 14 11 7 P5 4 15 12 12 15 12 8 P5 3 16 13 13 16 13 9 18 12...

Страница 73: ...39 31 28 39 31 19 27 13 P4 0 40 32 29 40 32 20 28 14 P6 3 41 41 P6 2 42 42 P6 1 43 43 P6 0 44 44 P1 4 45 33 30 45 33 21 1 P1 5 46 34 31 46 34 22 2 P1 6 47 35 32 47 35 23 3 P1 7 48 36 33 48 36 24 4 15...

Страница 74: ...input 3 pin ACMP1 ACMP1_N0 A Analog comparator 1 negative input 0 pin ACMP1_N1 Analog comparator 1 negative input 1 pin ACMP1_O O Analog comparator 1 output pin ACMP1_P0 A Analog comparator 1 positiv...

Страница 75: ...I External interrupt 0 input pin INT1 INT1 I External interrupt 1 input pin LCD LCD_COM0 O LCD Common 0 output LCD_COM1 O LCD Common 1 output LCD_COM2 O LCD Common 2 output LCD_COM3 O LCD Common 3 out...

Страница 76: ...utput LCD_SEG29 O LCD segment 29 output LCD_SEG30 O LCD segment 30 output LCD_SEG31 O LCD segment 31 output LCD_V1 I Input pin of the 1st most positive LCD level LCD_V2 I Input pin of the 2nd most pos...

Страница 77: ...1 MISO Master In Slave Out pin SPI1_MOSI I O SPI1 MOSI Master Out Slave In pin SPI1_SS I O SPI1 slave select pin STADC STADC I ADC external trigger input T0 T0 I O External count input to Timer Counte...

Страница 78: ...input pin UART3_TXD O UART3 data transmitter output pin VREF VREF A ADC reference voltage input Note This pin needs to be connected with a 1uF capacitor when use internal voltage reference output X32...

Страница 79: ...SPI1_MOSI SPI1_SS SPI1_SCK SPI1_MISO ICAP0 2 T1 T0 6 3 External VREF Max 64KB APROM Flash Max 4KB LDROM Flash Max Bytes Data Flash page 128B Clock Divider 24 MHz Internal RC Oscillator HIRC System Clo...

Страница 80: ...Memory The interrupt causes the CPU to jump to that location with where it commences execution of the interrupt service routine ISR External Interrupt 0 for example is assigned to location 0003H If Ex...

Страница 81: ...is 64KB 111 No LDROM APROM is 64 Kbytes 110 LDROM is 1 Kbytes APROM is 63 Kbytes 101 LDROM is 2 Kbytes APROM is 62 Kbytes 100 LDROM is 3 Kbytes APROM is 61 Kbytes 0xx LDROM is 4 Kbytes APROM is 60 Kb...

Страница 82: ...FH FF80H SPROM Non security mode SPROM Security mode FF80H FFFFH FFFEH 0xFF Others Figure 6 1 2 SPROM Memory Mapping And SPROM Security Mode 1 SPROM non secured mode the last byte is 0xFF The access b...

Страница 83: ...d the Unique Code only by IAP command More details please see Chapter 6 3 1 In application programming IAP IAP Mode IAPCN IAPA 15 0 IAPAH IAPAL IAPFD 7 0 IAPB 1 0 FOEN FCEN FCTRL 3 0 96 bit Unique Cod...

Страница 84: ...al RAM are present in all 80C51 devices The lowest 32 bytes as general purpose registers are grouped into 4 banks of 8 registers Program instructions call these registers as R0 to R7 Two bits RS0 and...

Страница 85: ...Accessing RAM 00H 07H 28H 08H 0FH 10H 17H 18H 1FH 20H 21H 22H 23H 24H 25H 26H 27H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 7FH 80H FFH 00H FFH Bit addressable General Purpose Registers General Purpose Registe...

Страница 86: ...ral hardware configuration bytes called CONFIG those are used to configure the hardware options such as the security bits system clock source and so on These hardware options can be re configured thro...

Страница 87: ...ues 4 OCDEN OCD Enable 1 OCD Disabled 0 OCD Enabled Note If MCU run in OCD debug mode and OCDEN 0 hard fault reset will disable Only HFIF flag be asserted 3 2 Reserved 1 LOCK Chip Lock Enable 1 Chip i...

Страница 88: ...1 0 LDSIZE 2 0 R W Factory default value 1111 1111b Bit Name Description 2 0 LDSIZE 2 0 LDROM Size Select Flash size is 64KB 111 No LDROM APROM is 64 Kbytes 110 LDROM is 1 Kbytes APROM is 63 Kbytes 10...

Страница 89: ...OD is 2 7V 010 VBOD is 3 0V 001 VBOD is 3 7V 000 VBOD is 4 4V 3 BOIAP Brown Out Inhibiting IAP This bit decides whether IAP erasing or programming is inhibited by brown out status This bit is valid on...

Страница 90: ...ption 7 4 WDTEN 3 0 WDT Enable This field configures the WDT behavior after MCU execution 1111 WDT is Disabled WDT can be used as a general purpose timer via software control 0101 WDT is Enabled as a...

Страница 91: ...user would like to modify a particular bit directly without changing other bits via bit field instructions All other SFR are byte addressable only The ML51 ML54 ML56 Series contains all the SFR prese...

Страница 92: ...e 0 MOV SFRS 01H switch to SFR Page 1 MOV SFRS 02H switch to SFR page 2 MOV SFRS 03H switch to SFR page 3 Timed Access Protection TA 6 1 7 2 The ML51 ML54 ML56 Series has several features such as WDT...

Страница 93: ...e first write of AAH then the timed access window is opened It remains open for 4 clock cycles during which user may write to the protected bits After 4 clock cycles this window automatically closes O...

Страница 94: ...ith wasting code size and low performance The ML51 ML54 ML56 Series provides two data pointers Thus software can load both a source and a destination address when doing a block move Once loading the s...

Страница 95: ...te Register SFR Address Reset Value DPL 82H All pages 0000_0000b 7 6 5 4 3 2 1 0 DPTR 7 0 R W Bit Name Description 7 0 DPTR 7 0 Data Pointer Low Byte This is the low byte of 16 bit data pointer DPL co...

Страница 96: ...set Value DPH 83H All pages 0000_0000b 7 6 5 4 3 2 1 0 DPTR 15 8 R W Bit Name Description 7 0 DPTR 15 8 Data Pointer High Byte This is the high byte of 16 bit data pointer DPH combined with DPL serve...

Страница 97: ...000b Others UUU0 0000b 7 6 5 4 3 2 1 0 SWRF RSTPINF HardF HardFInt GF2 0 DPS R W R W R W R W R W R R W Bit Name Description 3 GF2 General Purpose Flag 2 The general purpose flag that can be set or cle...

Страница 98: ...0FBS AUXR3 0 C0 I2C0CO N I2C0ADDR0 ADCRL ADCRH T3CON RL3 RH3 TA 1 CKDIV P3M1 P3M2 PWM0C4H PWM0C5H PORDIS 2 PWM2PL PWM2C0L PWM2C1L PWM2CON0 PWM2CON1 PWM2INTC 3 0 B8 IP SADEN0 SADEN1 SADDR1 I2C0DAT I2C0...

Страница 99: ...v 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual Pag e Add r 0 8 1 9 2 A 3 B 4 C 5 D 6 E 7 F 1 LIRCTRIM XLTCON CWKL 2 P6M1 P6M2 PWM1PH 3 Table 6...

Страница 100: ...D Data FCH 3 LCDDAT 7 0 00000000b SPI1SR Serial Peripheral Status Register FBH 0 SPIF WCOL SPIOVF MODF DISMODF DISSPIF TXBFF 00000000b PWM0MEN Pwm Mask Enable FBH 1 PMEN5 PMEN4 PMEN3 PMEN2 PMEN1 PMEN0...

Страница 101: ...H 2 P2MF1 3 0 P2MF0 3 0 00000000b F2H 3 DMA1TSR PDMA11 Transfer Status Register F1H 0 ACT HDONE FDONE 00000000b CAPCON3 F1H 1 P1MF76 P1 7 And P1 6 Multifunction Select F1H 2 P1MF7 3 0 P1MF6 3 0 000000...

Страница 102: ...S1 WLS0 TXDMAEN RXDMAEN CLKKEEP UARTEN 00000000b E7H 3 ADCCN Adc Current Sampling Number E6H 0 ADCCN 7 0 00000000b C1L Input Capture1 Low Byte E6H 1 C1L 7 0 00000000b SC1CR0 Sc1 Control Register 1 E6H...

Страница 103: ...u Rate Divide Rregister 1 DCH 2 SCDIV_2 SCDIV_1 SCDIV_0 ETURDIV_ 11 ETURDIV_ 10 ETURDIV_ 9 ETURDIV_8 00000000b DDH 3 SC0ETURD0 Sc0etu Rate Divider Register 0 DBH 0 ETURDIV 7 0 01110001b PWM0C1L Pwm0 C...

Страница 104: ...S0 OV P 00000000b ADCMPH Adc Compare High Byte CFH 0 ADCMP 11 4 00000000b CFH 1 CRVTEST I2C0ADDRM I2c0 Address Mask CFH 2 I2C0ADDRM 00000000b AUXR3 Auxiliary Register 3 CFH 3 UART3DG UART2DG UART1DG U...

Страница 105: ...Channel 1 Duty Low Byte C3H 2 PWM2C1 7 0 00000000b C3H 3 ADCRL Adc Result Low Byte C2H 0 ADCR_3 ADCR_2 ADCR_1 ADCR_0 00000000b P3M1 Port3 Mode Select 1 C2H 1 P3M1 7 P3M1 6 P3M1 5 P3M1 4 P3M1 3 P3M1 2...

Страница 106: ...AR Rtc Calendar Year Loading Register B7H 3 TENYEAR_ 3 TENYEAR_ 2 TENYEAR_ 1 TENYEAR_ 0 YEAR_3 YEAR_2 YEAR_1 YEAR_0 00000000b I2C1TOC I2c1 Timeout Counter B6H 0 I2TOCEN DIV I2TOF 00000000b P2M2 Port5...

Страница 107: ...SR P3 Slew Rate ADH 1 P3SR 7 P3SR 6 P3SR 5 P3SR 4 P3SR 3 P3SR 2 P3SR 1 P3SR 0 00000000b DMA3CNT PDMA13 Transfer Count ADH 2 DMA2CNT 7 0 00000000b RTCCALDAY Rtc Calendar Day Loading Register ADH 3 TEND...

Страница 108: ...QADJ 0 Rtc Frequency Compensation 0 Fraction Register A4H 3 FRACTION 00000000b BODCON0 Brownout Detection Control 0 A3H 0 BODEN BOV2 BOV1 BOV0 BOF BORST BORF BOS POR CCCCXC0X bBOD UUUUXU1X bOthers UUU...

Страница 109: ...Input 99H 1 P0SR 7 P0SR 6 P0SR 5 P0SR 4 P0SR 3 P0SR 2 P0SR 1 P0SR 0 00000000b PWM1PL Pwm Period Low Byte 99H 2 PWM1P 7 0 00000000b WDCONH Watchdog Timer Control High Byte 99H 3 WDPS 00000000b Y SCON...

Страница 110: ...P3DW 4 P3DW 3 P3DW 2 P3DW 1 P3DW 0 00000000b PWM1MEN Pwm Mask Data 8DH 2 PMEN1 PMEN0 00000000b DMA3CR1 PDMA1 3 Control Register 1 8DH 3 XOROUT REFOUT REFIN CRCEN 00000000b TH0 Timer 0 High Byte 8CH 0...

Страница 111: ...PTR 15 8 00000000b DPL Data Pointer Low Byte 82H A DPTR 7 0 00000000b SP Stack Pointer 81H A SP 7 0 00000111b P0 Port 0 80H A P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 P0 0 Outputlatch 00000000b Input XXXXXX...

Страница 112: ...01 2020 Page 112 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL All SFR Description 6 1 7 6 Note the reset value show as following means U unchanged C initialized by CONFIG X base o...

Страница 113: ...1111_1111 b P1 90H All pages Bit addressable 1111_1111 b P2 A0H All pages Bit addressable 1111_1111 b P3 B0H All pages Bit addressable 1111_1111 b P4 D8H All pages Bit addressable 1111_1111 b P5 B1H...

Страница 114: ...Value SP 81H All pages 0000_0111b 7 6 5 4 3 2 1 0 SP 7 0 R W Bit Name Description 7 0 SP 7 0 Stack Pointer The Stack Pointer stores the scratch pad RAM address where the stack begins It is incremente...

Страница 115: ...te Register SFR Address Reset Value DPL 82H All pages 0000_0000b 7 6 5 4 3 2 1 0 DPTR 7 0 R W Bit Name Description 7 0 DPTR 7 0 Data Pointer Low Byte This is the low byte of 16 bit data pointer DPL co...

Страница 116: ...set Value DPH 83H All pages 0000_0000b 7 6 5 4 3 2 1 0 DPTR 15 8 R W Bit Name Description 7 0 DPTR 15 8 Data Pointer High Byte This is the high byte of 16 bit data pointer DPH combined with DPL serve...

Страница 117: ...1 ML54 ML56 Series Technical Reference Manual RCTRIM0 High Speed Internal Oscillator Trim 0 TA Protected Register SFR Address Reset Value RCTRIM0 84H Page 0 TA protected XXXX_XXXXb 7 6 5 4 3 2 1 0 HIR...

Страница 118: ...HNICAL REFERENCE MANUAL RCTRIM1 High Speed Internal Oscillator Trim 1 TA Protected Register SFR Address Reset Value RCTRIM1 85H Page 0 TA protected XXXX_XXXXb 7 6 5 4 3 2 1 0 HIRCTRIM 0 R W Bit Name D...

Страница 119: ...CE MANUAL ML51 ML54 ML56 Series Technical Reference Manual LIRCTRIM Low Speed Internal Oscillator Trim TA Protected Register SFR Address Reset Value LIRCTRIM 84H Page 1 XXXX_XXXXb 7 6 5 4 3 2 1 0 LIRC...

Страница 120: ...11b 7 6 5 4 3 2 1 0 HSCH HXSG 2 0 LXSG 1 0 R W R W R W Bit Name Description 7 HSCH HXT Schmitt Trigger Select 0 disable 1 enable 6 4 HXSG 2 0 HXT Gain Value Select 000 L0 mode smallest value 001 L1 mo...

Страница 121: ...chnical Reference Manual RWKL Self Wake up Timer Reload Low Byte Register SFR Address Reset Value RWKL 86H Page 0 0000_0000b 7 6 5 4 3 2 1 0 RWK 7 0 R W Bit Name Description 7 0 RWK 7 0 WKT Reload Byt...

Страница 122: ...S TECHNICAL REFERENCE MANUAL CWKL Self Wake up Timer Current Count Value Low Byte Register SFR Address Reset Value CWKL 86H Page 1 0000_0000b 7 6 5 4 3 2 1 0 CWK 7 0 R Bit Name Description 7 0 CWK 7 0...

Страница 123: ...will be set as 1 after a power on reset It indicates a cold reset a power on reset complete This bit remains its value after any other resets This flag is recommended to be cleared via software 3 GF1...

Страница 124: ...ock stops and Program Counter PC suspends but all peripherals keep activated After CPU is woken up from Idle this bit will be automatically cleared via hardware and the program continue executing the...

Страница 125: ...ervice routine This bit can be set or cleared by software 4 TR0 Timer 0 Run Control 0 Timer 0 Disabled Clearing this bit will halt Timer 0 and the current count will be preserved in TH0 and TL0 1 Time...

Страница 126: ...719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL Bit Name Description 0 IT0 External Interrupt 0 Type Select This bit selects by which type that INT0 is triggered 0 INT0 is low level trig...

Страница 127: ...of the external pin T1 5 M1 Timer 1 Mode Select M1 M0 Timer 1 Mode 0 0 Mode 0 13 bit Timer Counter 0 1 Mode 1 16 bit Timer Counter 1 0 Mode 2 8 bit Timer Counter with auto reload from TH1 1 1 Mode 3...

Страница 128: ...SERIES TECHNICAL REFERENCE MANUAL TL0 Timer 0 Low Byte Register SFR Address Reset Value TL0 8AH Page 0 0000_0000b 7 6 5 4 3 2 1 0 TL0 7 0 R W Bit Name Description 7 0 TL0 7 0 Timer 0 Low Byte The TL0...

Страница 129: ...t Value P0DW 8AH Page 1 0000_0000 b P1DW 8BH Page 1 0000_0000 b P2DW 8CH Page 1 0000_0000 b P3DW 8DH Page 1 0000_0000 b P4DW 8EH Page 1 0000_0000 b P5DW 8FH Page 1 0000_0000 b P6DW 8FH Page 2 0000_000...

Страница 130: ...SERIES TECHNICAL REFERENCE MANUAL TL1 Timer 1 Low Byte Register SFR Address Reset Value TL1 8BH Page 0 0000_0000b 7 6 5 4 3 2 1 0 TL1 7 0 R W Bit Name Description 7 0 TL1 7 0 Timer 1 Low Byte The TL1...

Страница 131: ...MANUAL ML51 ML54 ML56 Series Technical Reference Manual TH0 Timer 0 High Byte Register SFR Address Reset Value TH0 8CH Page 0 0000_0000b 7 6 5 4 3 2 1 0 TH0 7 0 R W Bit Name Description 7 0 TH0 7 0 T...

Страница 132: ...RIES TECHNICAL REFERENCE MANUAL TH1 Timer 1 High Byte Register SFR Address Reset Value TH1 8DH Page 0 0000_0000b 7 6 5 4 3 2 1 0 TH1 7 0 R W Bit Name Description 7 0 TH1 7 0 Timer 1 High Byte The TH1...

Страница 133: ...1 Output Enable 0 Timer 1 output Disabled 1 Timer 1 output Enabled from T1 pin Note that Timer 1 output should be enabled only when operating in its Timer mode 4 T1M Timer 1 Clock Mode Select 0 The c...

Страница 134: ...it is set when WKT overflows If the WKT interrupt and the global interrupt are enabled setting this bit will make CPU execute WKT interrupt service routine This bit is not automatically cleared via ha...

Страница 135: ...cal Reference Manual SFRS SFR Page Selection Register SFR Address Reset Value SFRS 91H All pages 0000_0000b 7 6 5 4 3 2 1 0 SFRPAGE 1 0 R W Bit Name Description 1 0 SFRPAGE 1 0 SFR Page Select 00 Inst...

Страница 136: ...iperal source selected Note 0001 0011 1010 peripheral devices to XRAM memory 0101 0111 1110 XRAM memory to peripheral devices 3 HIE PDMA HALFTransfer Done Interrupt Enable Bit 0 Interrupt Disabled whe...

Страница 137: ...SFR Address Reset Value P0UP 92H Page 1 0000_0000 b P1UP 93H Page 1 0000_0000 b P2UP 94H Page 1 0000_0000 b P3UP 95H Page 1 0000_0000 b P4UP 96H Page 1 0000_0000 b P5UP 97H Page 1 0000_0000 b 7 6 5 4...

Страница 138: ...e 0 0000_0000 b DMA1MAL ECH Page 0 0000_0000 b DMA2MAL B4H Page 2 0000_0000 b DMA3MAL ACH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 MAL 7 0 R W Bit Name Description 7 0 MAL 7 0 PDMA XRAM Base Address Low Byt...

Страница 139: ...nCNT PDMA Transfer Count Register SFR Address Reset Value DMA0CNT 94H Page 0 0000_0000 b DMA1CNT EDH Page 0 0000_0000 b DMA2CNT B5H Page 2 0000_0000 b DMA3CNT ADH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 DM...

Страница 140: ...H Page 2 0000_0000 b DMA3CCNT AEH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 DMAnCCNT 7 0 R Bit Name Description 7 0 DMAnCCNT 7 0 PDMA Current Transfer Count The current transfer count for PDMA request operat...

Страница 141: ...oscillator is not stable or disabled 1 High speed internal oscillator is enabled and stable 4 LIRCST Low Speed Internal Oscillator 38 4 kHz Status 0 Low speed internal oscillator is not stable or is...

Страница 142: ...enabled by setting IAPEN CHPCON 0 the high speed internal 24 MHz oscillator will be enabled automatically The hardware will also set HIRCEN and HIRCST bits After IAPEN is cleared HIRCEN and EHRCST res...

Страница 143: ...de 0 This bit select the baud rate between FSYS 12 and FSYS 2 0 The clock runs at FSYS 12 baud rate It maintains standard 8051compatibility 1 The clock runs at FSYS 2 baud rate for faster serial commu...

Страница 144: ...al port 0 after the 8th bit in Mode 0 or the last data bit in other modes When the serial port 0 interrupt is enabled setting this bit causes the CPU to execute the serial port 0 interrupt service rou...

Страница 145: ...b 7 6 5 4 3 2 1 0 SBUF 7 0 R W Bit Name Description 7 0 SBUF 7 0 Serial Port 0 Data Buffer This byte actually consists two separate registers One is the receiving resister and the other is the transm...

Страница 146: ...0_0000 b P1S 9BH Page 1 0000_0000 b P2S 9DH Page 1 0000_0000 b P3S ACH Page 1 0000_0000 b P4S BBH Page 1 0000_0000 b P5S BFH Page 1 0000_0000 b P6S 96H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 PnS 7 PnS 6 P...

Страница 147: ...ected POR 0000_0001 b WDT 0000_000U b Others 0000_000U b 7 6 5 4 3 2 1 0 WDPS 3 R W Bit Name Description 7 1 Reserved 0 WDPS 3 WDT Clock Pre Scalar Select These bits determine the pre scale of WDT clo...

Страница 148: ...7 0 R W Bit Name Description 7 0 SBUF1 7 0 Serial Port 1 Data Buffer This byte actually consists two separate registers One is the receiving resister and the other is the transmitting buffer When data...

Страница 149: ...0SR 9AH Page 1 0000_0000 b P1SR 9CH Page 1 0000_0000 b P2SR 9EH Page 1 0000_0000 b P3SR ADH Page 1 0000_0000 b P4SR BCH Page 1 0000_0000 b P5SR AEH Page 1 0000_0000 b P6SR 8EH Page 2 0000_0000 b 7 6 5...

Страница 150: ...e Fault Brake Interrupt 0 Fault Brake interrupt Disabled 1 Fault Brake interrupt Enable When interrupt generated FBF PWM0FBD 7 set 1 4 EWDT Enable WDT Interrupt 0 WDT interrupt Disabled 1 WDT interrup...

Страница 151: ...nerated SI I2C1CON 3 or I2TOF I2C1TOC 0 set 1 4 ESPI1 Enable SPI1 Interrupt 0 SPI1 interrupt Disabled 1 SPI1 interrupt Enable When interrupt generated SPIF SP2SR 7 MODF SP2SR 4 or SPIOVF SP2SR 5 set 1...

Страница 152: ...e 0 to clear this bit 6 PORF POR Reset Flag 1 POR15 Reset Flag is active 0 POR15 Reset Flag is inactive Write 0 to clear this bit 5 HFRF mirrored From AUXR0 5 Clear this bit by write AUXR0 5 0 or RSR...

Страница 153: ...following condition is met 1 The accessing address is oversize 2 IAPCN command is invalid 3 IAP erases or programs updating un enabled block 4 IAP erasing or programming operates under VBOD while BOIA...

Страница 154: ...parator is enabled The ADC result can be read While this flag is 1 ADC cannot start a new converting This bit is cleared by software 6 ADCS A D Converting Software Start Trigger Setting this bit 1 tri...

Страница 155: ...Converting Channel Select This filed selects the activating analog input source of ADC If ADCEN is 0 all inputs are disconnected 0000 ADC_CH0 0001 ADC_CH1 0010 ADC_CH2 0011 ADC_CH3 0100 ADC_CH4 0101...

Страница 156: ...000_0000 b PIPS5 A6H Page 1 0000_0000 b PIPS6 A7H Page 1 0000_0000 b PIPS7 AFH Page 1 0000_0000 b 7 6 5 4 3 2 1 0 PSEL 2 0 BSEL 2 0 R W R W Bit Name Description 7 Reserved 6 4 PSEL 2 0 Pin Interrupt C...

Страница 157: ...d via software 5 HFRF Hard Fault Reset Flag Once CPU fetches instruction address over Flash size while EHFI EIE1 4 0 MCU will reset and this bit will be set via hardware It is recommended that the fla...

Страница 158: ...is 1 8V 101 VBOD is 2 0V 100 VBOD is 2 4V 011 VBOD is 2 7V 010 VBOD is 3 0V Following setting value only for ML51 32KB Flash series 001 VBOD is 3 7V 000 VBOD is 4 4V 3 BOF Brown Out Interrupt Flag Thi...

Страница 159: ...DD voltage level comparing with VBOD while BOD circuit is enabled It keeps 0 if BOD is not enabled 0 VDD voltage level is higher than VBOD or BOD is disabled 1 VDD voltage level is lower than VBOD Not...

Страница 160: ...Go IAP begins by setting this bit as logic 1 After this instruction the CPU holds the Program Counter PC and the IAP hardware automation takes over to control the progress After IAP action completed t...

Страница 161: ...f80 0xffff is mapping to APROM memory 1 CPU memory address 0xff80 0xffff is mapping to SPROM memory 3 SPUEN SPROM Memory Space Updated Enable TA Protected 0 Inhibit erasing or programming SPRO Mbytes...

Страница 162: ...L56 SERIES TECHNICAL REFERENCE MANUAL IAPAL IAP Address Low Byte Register SFR Address Reset Value IAPAL A6H Page 0 0000 _0000 b 7 6 5 4 3 2 1 0 IAPA 7 0 R W Bit Name Description 7 0 IAPA 7 0 IAP Addre...

Страница 163: ...NCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual IAPAH IAP Address High Byte Register SFR Address Reset Value IAPAH A7H Page 0 0000 _0000 b 7 6 5 4 3 2 1 0 IAPA 15 8 R W Bit Name Descriptio...

Страница 164: ...1 5 EBOD Enable Brown Out Interrupt 0 Brown out detection interrupt Disabled 1 Brown out detection interrupt Enable When interrupt generated BOF BODCON0 3 set 1 4 ES Enable Serial Port 0 Interrupt 0...

Страница 165: ...nical Reference Manual SADDRn UART Slave Address Register SFR Address Reset Value SADDR0 A9H Page 0 0000 _0000 b SADDR1 BBH Page 0 0000 _0000 b 7 6 5 4 3 2 1 0 SADDRn 7 0 R W Bit Name Description 7 0...

Страница 166: ...L 2 0 Internal VREF Output Voltage Select This field selects VREF output voltage 000 1 538V when VDD 2 0V 001 2 048V when VDD 2 4V 010 2 560V when VDD 2 9V 011 3 072V when VDD 3 4V 100 4 096V when VDD...

Страница 167: ...ng and reading WDCLR bit is different Writing 0 No effect 1 Clearing WDT counter Reading 0 WDT counter is completely cleared 1 WDT counter is not yet cleared 5 WDTF WDT Time Out Flag This bit indicate...

Страница 168: ...IES TECHNICAL REFERENCE MANUAL Bit Name Description Note WDTRF will be cleared after power on reset be set after WDT reset and remains unchanged after any other resets WDPS 3 0 are all set after power...

Страница 169: ...F Trim Select TA Protected Register SFR Address Reset Value VRFTRIM AAH Page 1 TA protected 0100_0000b 7 6 5 4 3 2 1 0 VRFTRIM 6 0 R W Address AAH Page 1 Reset value 0100 0000b Bit Name Description 7...

Страница 170: ...w power mode 2 by turning on BOD circuit every 6 4 ms periodically 11 BOD low power mode 3 by turning on BOD circuit every 25 6 ms periodically 0 BODFLT BOD Filter Control BOD has a filter which count...

Страница 171: ...ed propagation delay 0 6us 10uA typ 11 fast speed propagation delay 0 2us 75uA typ 5 POE1 Analog Comparator 1 Polarity Output Enable 0 ACMP1 output directly 1 ACMP1 output inversely 4 POE0 Analog Comp...

Страница 172: ...RTC RTC interrupt priority low bit 6 PDMA3 PDMA3 interrupt priority low bit 5 PDMA2 PDMA2 interrupt priority low bit 4 SMC1 SMC1 interrupt priority low bit 3 TK Touch Key interrupt priority low bit 2...

Страница 173: ...Name Description 7 RTCH RTCH interrupt priority high bit 6 PDMA3H PDMA3H interrupt priority high bit 5 PDMA2H PDMA2H interrupt priority high bit 4 SMC1H SMC1H interrupt priority high bit 3 TKH Touch...

Страница 174: ...AEH Page 0 0000 _0000 b 7 6 5 4 3 2 1 0 IAPFD 7 0 R W Bit Name Description 7 0 IAPFD 7 0 IAP Flash Data This byte contains Flash data which is read from or is going to be written to the Flash Memory U...

Страница 175: ...FCTRL 3 0 R W R W R W R W Bit Name Description 7 6 IAPB 1 0 IAP Control This byte is used for IAP command For details see Figure 6 3 1 IAP Modes and Command Codes 5 FOEN This Byte is Used for IAP Com...

Страница 176: ...ue P0M1 B1H Page 1 1111_1111 b P1M1 B3H Page 1 1111_1111 b P2M1 B5H Page 1 1111_1111 b P3M1 C2H Page 1 1111_1111 b P4M1 B9H Page 1 1111_1111 b P5M1 BDH Page 1 1111_1111 b P6M1 84H Page 2 1111_1111 b 7...

Страница 177: ...00_0000 b P2M2 B6H Page 1 0000_0000 b P3M2 C3H Page 1 0000_0000 b P4M2 BAH Page 1 0000_0000 b P5M2 BEH Page 1 0000_0000 b P6M2 85H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 PnM2_7 PnM2_6 PnM2_5 PnM2_4 PnM2_3...

Страница 178: ...byte of the I2 C data to be transmitted or a byte which has just received Data in I2CnDAT remains as long as SI is logic 1 The result of reading or writing I2CnDAT during I2 C transceiver progress is...

Страница 179: ...Reserved 5 4 INTTYP 1 0 PWM Interrupt Type Select These bit select PWM interrupt type 00 Falling edge on PWMn_CH0 1 2 3 4 5 pin 01 Rising edge on PWMn_CH0 1 2 3 4 5 pin 10 Central point of a PWM perio...

Страница 180: ...eserved 6 PADC ADC interrupt priority low bit 5 PBOD Brown out detection interrupt priority low bit 4 PS Serial port 0 interrupt priority low bit 3 PT1 Timer 1 interrupt priority low bit 2 PX1 Externa...

Страница 181: ...Register SFR Address Reset Value SADEN0 B9H Page 0 0000_0000 b SADEN1 BAH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 SADENn 7 0 R W Bit Name Description 7 0 SADENn 7 0 Slave n Address Mask This byte is a mas...

Страница 182: ...nDAT contains a byte of the I 2 C data to be transmitted or a byte which has just received Data in I2CnDAT remains as long as SI is logic 1 The result of reading or writing I2CnDAT during I 2 C transc...

Страница 183: ...I2CnSTAT 7 3 0 0 0 R R R R Bit Name Description 7 3 I2CnSTAT 7 3 I2Cn Status Code The MSB five bits of I2CnSTAT contains the status code There are 27 possible status codes When I2CnSTAT is F8H no rele...

Страница 184: ...Reset value 0000 1001b Bit Name Description 7 0 I2CnCLK 7 0 I2Cn Clock Setting In master mode This register determines the clock rate of I 2 C bus when the device is in a master mode The clock rate f...

Страница 185: ...0_0000 b 7 6 5 4 3 2 1 0 UART3DG UART2DG UART1DG UART0DG R W R W R W R W Bit Name Description 7 4 Reserved 3 UART3DG UART3 RX Deglitch Control 1 Deglitch is Enabled 0 Deglitch is Disabled 2 UART2DG UA...

Страница 186: ...1 0 I2TOCEN DIV I2TOF R W R W R W Bit Name Description 7 3 Reserved 2 I2TOCEN I2Cn Time Out Counter Enable 0 I 2 C time out counter Disabled 1 I 2 C time out counter Enabled 1 DIV I2Cn Time Out Counte...

Страница 187: ...ML54 ML56 Series Technical Reference Manual CWKH Self Wake up Timer Current Count Value High Byte Register SFR Address Reset Value CWKH BEH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 CWK 15 8 R W Bit Name De...

Страница 188: ...H Self Wake up Timer Reload High Byte Register SFR Address Reset Value RWKH BFH Page 2 0000 0000b 7 6 5 4 3 2 1 0 RWK 15 8 R W Bit Name Description 7 0 RWK 15 8 WKT Reload High Byte It holds the 16 bi...

Страница 189: ...following If STA is set while the I 2 C is already in the master mode and one or more bytes have been transmitted or received the I 2 C generates a repeated START condition Note that STA can be set an...

Страница 190: ...ert Flag If the AA flag is set an ACK low level on SDA will be returned during the acknowledge clock pulse of the SCL line while the I 2 C device is a receiver or an own address matching slave If the...

Страница 191: ...Own Slave Address In master mode These bits have no effect In slave mode These 7 bits define the slave address of this I 2 C device by user The master should address I 2 C device by sending the same a...

Страница 192: ...lock Divider Register SFR Address Reset Value CKDIV C1H Page 1 0000_0000b 7 6 5 4 3 2 1 0 CKDIV 7 0 R W Bit Name Description 7 0 CKDIV 7 0 Clock Divider The system clock frequency FSYS follows the equ...

Страница 193: ...ML51 ML54 ML56 Series Technical Reference Manual ADCRL ADC Result Low Byte Register SFR Address Reset Value ADCRL C2H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCR 3 0 R Bit Name Description 7 4 Reserved 3...

Страница 194: ...High Byte This byte with PWMnCxL controls the duty of the output signal PGx from PWM generator Register SFR Address Reset Value PWM0C0H D2H Page 1 0000_0000 b PWM0C1H D3H Page 1 0000_0000 b PWM0C2H D4...

Страница 195: ...NUAL ML51 ML54 ML56 Series Technical Reference Manual ADCRH ADC Result High Byte Register SFR Address Reset Value ADCRH C3H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCR 11 4 R Bit Name Description 7 0 ADCR...

Страница 196: ...t 5 BRCK Serial Port 0 Baud Rate Clock Source This bit selects which Timer is used as the baud rate clock source when serial port 0 is in Mode 1 or 3 0 Timer 1 1 Timer 3 4 TF3 Timer 3 Overflow Flag Th...

Страница 197: ...RENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual RL3 Timer 3 Reload Low Byte Register SFR Address Reset Value RL3 C5H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 RL3 7 0 R W Bit Name Description 7...

Страница 198: ...6 SERIES TECHNICAL REFERENCE MANUAL RH3 Timer 3 Reload High Byte Register SFR Address Reset Value RH3 C6H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 RH3 15 8 R W Bit Name Description 7 0 RH3 15 8 Timer 3 Relo...

Страница 199: ...ical Reference Manual PORDIS POR Disable TA Protected Register SFR Address Reset Value PORDIS C6H Page 1 TA protected 0000_0000 b 7 6 5 4 3 2 1 0 PORDIS 7 0 W Bit Name Description 7 0 PORDIS 7 0 POR D...

Страница 200: ...7 6 5 4 3 2 1 0 TA 7 0 W Bit Name Description 7 0 TA 7 0 Timed Access The timed access register controls the access to protected SFR To access protected bits user should first write AAH to the TA and...

Страница 201: ...mer 2 overflows or a compare match occurs If the Timer 2 interrupt and the global interrupt are enable setting this bit will make CPU execute Timer 2 interrupt service routine This bit is not automati...

Страница 202: ...512 3 CAPCR Capture Auto Clear This bit is valid only under Timer 2 auto reload mode It enables hardware auto clearing TH2 and TL2 counter registers after they have been transferred in to RCMP2H and...

Страница 203: ...situation and no warning alarms 2 UART2PX Serial Port 2 RX SMC0 DATA TX SMC0 CLK Pin Exchange 0 Assign UART2 RXD SMC0 DATA to multiple I O pin RXD UART2 TXD SMC CLK to multiple I O pin TXD 1 Assign U...

Страница 204: ...I O pin RXD UART0 TXD to multiple I O pin TXD 1 Assign UART0 RXD to multiple I O pin TXD UART0 TXD to multiple I O pin RXD Note that Pin direction is controlled by I O type of relative pin RXD TXD wil...

Страница 205: ...R level R W edge R level R W edge R level R W edge R level R W edge R level R W edge R level R W edge R level R W edge Bit Name Description 7 0 PIFn Pin Interrupt Channel n Flag If the edge trigger is...

Страница 206: ...Low Byte Register SFR Address Reset Value RCMP2L CAH Page 1 0000_0000 b 7 6 5 4 3 2 1 0 RCMP2 7 0 R W Bit Name Description 7 0 RCMP2 7 0 Timer 2 Reload Compare Low Byte This register stores the low b...

Страница 207: ...e Manual ADCBAL ADC RAM Base Address Low Byte Register SFR Address Reset Value ADCBAL CBH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCBAL 7 0 R W Bit Name Description 7 0 ADCBAL 7 0 ADC RAM Base Address Low...

Страница 208: ...gh Byte Register SFR Address Reset Value RCMP2H CBH Page 1 0000_0000 b 7 6 5 4 3 2 1 0 RCMP2 15 8 R W Bit Name Description 7 0 RCMP2 15 8 Timer 2 Reload Compare High Byte This register stores the high...

Страница 209: ...CE MANUAL ML51 ML54 ML56 Series Technical Reference Manual TL2 Timer 2 Low Byte Register SFR Address Reset Value TL2 CCH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 T2 7 0 R W Bit Name Description 7 0 T2 7 0 T...

Страница 210: ...RIES TECHNICAL REFERENCE MANUAL TH2 Timer 2 High Byte Register SFR Address Reset Value TH2 CDH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 T2 15 8 R W Bit Name Description 7 0 T2 15 8 Timer 2 High Byte The TH2...

Страница 211: ...4 ML56 Series Technical Reference Manual ADCMPL ADC Compare Low Byte Register SFR Address Reset Value ADCMPL CEH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCMP 3 0 W R Bit Name Description 7 4 Reserved 3 0...

Страница 212: ...FR Address Reset Value AINDIDS0 CEH Page 1 0000_0000 b 7 6 5 4 3 2 1 0 AIN7DIDS AIN6DIDS AIN5DIDS AIN4DIDS AIN3DIDS AIN2DIDS AIN1DIDS AIN0DIDS R W R W R W R W R W R W R W R W Bit Name Description 7 0...

Страница 213: ...Digital Input Disconnect Register SFR Address Reset Value AINDIDS1 CEH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 AIN15DIDS AIN14DIDS AIN13DIDS AIN12DIDS AIN11DIDS AIN10DIDS R W R W R W R W R W R W Bit Name D...

Страница 214: ...AL REFERENCE MANUAL PWM0FBS PWM Brake Source Select Register SFR Address Reset Value PWM0FBS CEH Page 3 0000_0000 b 7 6 5 4 3 2 1 0 PWM0FBS R W Bit Name Description 1 0 PWM0FBS PWM Brake Source Select...

Страница 215: ...1 ML54 ML56 Series Technical Reference Manual ADCMPH ADC Compare High Byte Register SFR Address Reset Value ADCMPH CFH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCMP 11 4 W R Bit Name Description 7 0 ADCMP...

Страница 216: ...I2CnADDRM I2Cn Address Mask Register SFR Address Reset Value I2C0ADDRM CFH Page 2 0000_0000 b I2C1ADDRM D7H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 Mask Bit 7 Mask Bit 6 Mask Bit 5 Mask Bit 4 Mask Bit 3 Ma...

Страница 217: ...0 The general purpose flag that can be set or cleared by user 4 RS1 Register Bank Selection Bits These two bits select one of four banks in which R0 to R7 locate RS1 RS0 Register Bank RAM Address 0 0...

Страница 218: ...HNICAL REFERENCE MANUAL Bit Name Description 1 F1 User Flag 1 The general purpose flag that can be set or cleared by user via software 0 P Parity Flag Set to 1 to indicate an odd number of ones in the...

Страница 219: ...the loading is complete LOAD will be automatically cleared via hardware The meaning of writing and reading LOAD bit is different Writing 0 No effect 1 Load new period and duty in their buffers while a...

Страница 220: ...After the loading is complete LOAD will be automatically cleared via hardware The meaning of writing and reading LOAD bit is different Writing 0 No effect 1 Load new period and duty in their buffers w...

Страница 221: ...anual PWMnPH PWM Period High Byte Register SFR Address Reset Value PWM0PH D1H Page 1 0000_0000 b PWM1PH 86H Page 2 0000_0000 b PWM2PH B9H Page 2 0000_0000 b PWM3PH C9H Page 2 0000_0000 b 7 6 5 4 3 2 1...

Страница 222: ...mparator 0 Negative Input Selection 00 ACMP0_N0 P2 4 pin 01 Internal comparator reference voltage CRV 10 VBG Band gap 11 ACMP0_N1 P2 0 pin 3 WKEN Comparator 0 Power Down Wake Up Enable Bit 0 Comparato...

Страница 223: ...3 P3 0 pin 5 4 NEGSEL Comparator 1 Negative Input Selection 00 ACMP1_N0 P2 2 pin 01 Internal comparator reference voltage CRV 10 VBG Band gap 11 ACMP1_N1 P3 1 pin 3 WKEN Comparator 1 Power Down Wake U...

Страница 224: ...red to 0 Note This bit is read only 2 ACMP1IF Comparator 1 Interrupt Flag This bit is set by hardware whenever the comparator 1 output changes state This will generate an interrupt if ACMPIE ACMPCR1 1...

Страница 225: ...e Voltage Control Register Register SFR Address Reset Value ACMPVREF D5H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 CRV1CTL 2 0 CRV0CTL 2 0 R W R W Bit Name Description 7 Reserved 6 4 CRV1CTL 2 0 Comparator 1...

Страница 226: ...bit length of block guard time According to ISO7816 3 in T 0 mode the software must clear T bit to 0 for real block guard time 16 5 In T 1 mode the software must set T bit to 1 for real block guard t...

Страница 227: ...tion the setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F After hardware received first data and stored it at buffer hardware will decided the convention...

Страница 228: ...PWM Negative Polarity Register SFR Address Reset Value PWM0NP D6H Page 1 0000_0000 b 7 6 5 4 3 2 1 0 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0 R W R W R W R W R W R W Bit Name Description 5 0 PNPn PWMn Negative P...

Страница 229: ...checked between the last data word bit and stop bit of the serial data 1 Parity bit is not generated transmitting data or checked receiving data during transfer Note In smart card mode this field mus...

Страница 230: ...0 UARTEN UART Mode Enable Bit 0 Smart Card mode 1 UART mode Note 1 When operating in UART mode user must set CONSEL SCnCR0 4 0 and AUTOCEN SCnCR0 3 0 Note 2 When operating in Smart Card mode user must...

Страница 231: ...R W R W R W Bit Name Description 7 FBF Fault Brake Flag This flag is set when FBINEN is set as 1 and FB pin detects an edge which matches FBINLS PWM0FBD 6 selection This bit is cleared by software Aft...

Страница 232: ...0000_0000 b SC1DR D9H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 SCnDR 7 0 R W Bit Name Description 7 0 SCnDR 7 0 SC UART Buffer Data This byte is used for transmitting or receiving data on SC UART bus A writ...

Страница 233: ...Manual PWMnPL PWM Period Low Byte Register SFR Address Reset Value PWM0PL D9H Page 1 0000_0000 b PWM1PL 99H Page 2 0000_0000 b PWM2PL C1H Page 2 0000_0000 b PWM3PL D1H Page 2 0000_0000 b 7 6 5 4 3 2 1...

Страница 234: ...UAL SCnEGT SC Extra Guard Time Register Register SFR Address Reset Value SC0EGT DAH Page 0 0000_0000 b SC1EGT DAH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 SCnEGT 7 0 R W Bit Name Description 7 0 SCnEGT 7 0...

Страница 235: ...0 1 2 3 4 5 PWMnCx Duty Low Byte This byte with PWMnCxH controls the duty of the output signal PGx from PWM generator Register SFR Address Reset Value PWM0C0L DAH Page 1 0000_0000 b PWM0C1L DBH Page 1...

Страница 236: ...ss Reset Value SC0ETURD0 DBH Page 0 0111_0011 b SC1ETURD0 DBH Page 2 0111_0011 b 7 6 5 4 3 2 1 0 ETURDIV 7 0 R W Bit Name Description 7 0 ETURDIV 7 0 LSB Bits of ETU Rate Divider The field indicates t...

Страница 237: ...W R W Bit Name Description 7 Reserved 6 4 SCDIV 2 0 SC Clock Divider 000 FSC is FSYS 1 001 FSC is FSYS 2 010 FSC is FSYS 4 011 FSC is FSYS 8 By default 100 FSC is FSYS 16 101 FSC is FSYS 16 110 FSC i...

Страница 238: ...ock guard time interrupt Disabled 1 Block guard time interrupt Enabled 2 TERRIEN Transfer Error Interrupt Enable Bit This field is used to enable transfer error interrupt The transfer error states is...

Страница 239: ...2 TERRIF Transfer Error Interrupt Status Flag Read Only This field is used for transfer error interrupt status flag The transfer error states is at SC0TSR register which includes receiver break error...

Страница 240: ...e received character does not have a valid stop bit that is the stop bit following the last data bit or parity bit is detected as logic 0 Note This bit is read only but it can be cleared by writing 0...

Страница 241: ...L56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual Bit Name Description 0 RXOV RX Overflow Error Status Flag Read Only This bit is set when RX buffer overflow Note...

Страница 242: ...up Mode Enable This bit enables the group mode If enabled the duty of first three pairs of PWM are decided by PWM01H and PWM01L rather than their original duty Register Description 0 Group mode Disabl...

Страница 243: ...L56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual Bit Name Description 2 0 PWMDIV 2 0 PWM Clock Divider This field decides the pre scale of PWM clock source 000 1...

Страница 244: ...or Bit addressable Register SFR Address Reset Value ACC E0H All pages Bit addressable 0000_0000 b 7 6 5 4 3 2 1 0 ACC 7 ACC 6 ACC 5 ACC 4 ACC 3 ACC 2 ACC 1 ACC 0 R W R W R W R W R W R W R W R W Bit Na...

Страница 245: ...is set while total A D conversions are completed 3 2 ETGTYP 1 0 External Trigger Type Select When ADCEX ADCCON1 1 is set these bits select which condition triggers ADC conversion 00 Falling edge on PW...

Страница 246: ...Capture 1 Enable 0 Input capture channel 1 Disabled 1 Input capture channel 1 Enabled 4 CAPEN0 Input Capture 0 Enable 0 Input capture channel 0 Disabled 1 Input capture channel 0 Enabled 3 Reserved 2...

Страница 247: ...atch the condition of ADC compare value defined ADCF will be set to 1 This condition base on ADCMPH ADCMPL and ADCMPOP register define The ADCF register changes to 1 only when ADC comparing result mat...

Страница 248: ...P1LS 1 0 CAP0LS 1 0 R W R W R W Bit Name Description 7 6 Reserved 5 4 CAP2LS 1 0 Input Capture 2 Level Select 00 Falling edge 01 Rising edge 10 Either rising or falling edge 11 Reserved 3 2 CAP1LS 1 0...

Страница 249: ...W Bit Name Description 7 0 ADCDLY 7 0 ADC External Trigger Delay Counter Low Byte This 8 bit field combined with ADCCON2 0 forms a 9 bit counter This counter inserts a delay after detecting the extern...

Страница 250: ...Reserved 6 ENF2 Enable Noise Filer on Input Capture 2 0 Noise filter on input capture channel 2 Disabled 1 Noise filter on input capture channel 2 Enabled 5 ENF1 Enable Noise Filer on Input Capture 1...

Страница 251: ...l ADCBAH ADC RAM Base Address High Byte Register SFR Address Reset Value ADCBAH E4H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCBA 11 8 R W Bit Name Description 7 4 Reserved 3 0 ADCBA 11 8 ADC RAM Base Addr...

Страница 252: ...ure Low Byte n 0 1 2 Register SFR Address Reset Value C0L E4H Page 1 0000_0000 b C1L E6H Page 1 0000_0000 b C2L EDH Page 1 0000_0000 b 7 6 5 4 3 2 1 0 CnL 7 0 R W Bit Name Description 7 0 CnL 7 0 Inpu...

Страница 253: ...54 ML56 Series Technical Reference Manual ADCSN ADC Sampling Number Register SFR Address Reset Value ADCSN E5H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCSN 7 0 R W Bit Name Description 7 0 ADCSN 7 0 ADC S...

Страница 254: ...n High Byte n 1 2 3 Register SFR Address Reset Value C0H E5H Page 1 0000_0000 b C1H E7H Page 1 0000_0000 b C2H EEH Page 1 0000_0000 b 7 6 5 4 3 2 1 0 CnH 7 0 R W Bit Name Description 7 0 CnH 7 0 Inpu...

Страница 255: ...ies Technical Reference Manual ADCCN ADC Current Sampling Number Register SFR Address Reset Value ADCCN E6H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCCN 7 0 R Bit Name Description 7 0 ADCCN 7 0 ADC Curren...

Страница 256: ...010 FADC is FSYS 4 011 FADC is FSYS 8 100 FADC is FSYS 16 101 FADC is FSYS 32 110 FADC is FSYS 64 111 FADC is FSYS 128 3 Reserved 2 CMPHIT ADC Comparator Hit Flag This bit is set by hardware when ADCM...

Страница 257: ...7 6 5 4 3 2 1 0 ACT HDONE FDONE R R W R W Bit Name Description 7 3 Reserved 2 ACT PDMA in Active Status Flag Read Only 0 This bit is cleared automatically when PDMA transfer is done or disabled 1 This...

Страница 258: ...l triggered 1 Edge triggered 5 PIT5 Pin Interrupt Channel 5 Type Select This bit selects which type that pin interrupt channel 5 is triggered 0 Level triggered 1 Edge triggered 4 PIT4 Pin Interrupt Ch...

Страница 259: ...54 ML56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual Bit Name Description 0 PIT0 Pin Interrupt Channel 0 Type Select This bit selects which type that pin interrup...

Страница 260: ...t Value MTM0DA EAH Page 0 0000_0000 b MTM1DA F2H Page 0 0000_0000 b MTM2DA B7H Page 2 0000_0000 b MTM3DA AFH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 MTMnDA 7 0 R W Bit Name Description 7 0 MTMnDA 7 0 Memor...

Страница 261: ...age 1 0000_0000 b 7 6 5 4 3 2 1 0 PINEN7 PINEN6 PINEN5 PINEN4 PINEN3 PINEN2 PINEN1 PINEN0 R W R W R W R W R W R W R W R W Bit Name Description 7 0 PINENn Pin Interrupt Channel n Negative Polarity Enab...

Страница 262: ...ML51 ML54 ML56 Sep 01 2020 Page 262 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL...

Страница 263: ...age 1 0000_0000 b 7 6 5 4 3 2 1 0 PIPEN7 PIPEN6 PIPEN5 PIPEN4 PIPEN3 PIPEN2 PIPEN1 PIPEN0 R W R W R W R W R W R W R W R W Bit Name Description 7 0 PIPENn Pin Interrupt Channel n Positive Polarity Enab...

Страница 264: ...imer 2 interrupt priority low bit 6 PSPI0 SPI0 interrupt priority low bit 5 PFB Fault Brake interrupt priority low bit 4 PWDT WDT interrupt priority low bit 3 PPWM0 PWM interrupt priority low bit 2 PC...

Страница 265: ...Manual B B Register Bit addressable Register SFR Address Reset Value B F0H All pages Bit addressable 0000_0000 b 7 6 5 4 3 2 1 0 B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 R W R W R W R W R W R W R W R W Bit Nam...

Страница 266: ...dress Reset Value LCDCPUMP F1H Page 3 0000_0000 b 7 6 5 4 3 2 1 0 VCP_SEL 5 0 R W Address F1H Page 3 Reset value 0000 0000b Bit Name Description 7 6 Reserved 5 0 VCP_SEL 5 0 Charge Pump Voltage Set 00...

Страница 267: ...es low for each transmission when selecting external Slave device and goes high during each idle state to de select the Slave device 6 SPIEN SPI Enable 0 SPI function Disabled 1 SPI function Enabled 5...

Страница 268: ...12M bit s 0 0 0 1 4 6M bit s 0 0 1 0 8 3M bit s 0 0 1 1 16 1 5M bit s 0 1 0 0 32 750k bit s 0 1 0 1 64 375k bit s 0 1 1 0 128 187k bit s 0 1 1 1 256 93 7k bit s 1 0 0 0 3 8M bit s 1 0 0 1 6 4M bit s...

Страница 269: ...of SPI clock divider The clock rates below are illustrated under FSYS 24 R W condition SPR3 SPR2 SPR1 SPR0 Divider SPI clock rate 0 0 0 0 2 12M bit s 0 0 0 1 4 6M bit s 0 0 1 0 8 3M bit s 0 0 1 1 16 1...

Страница 270: ...d 2 RXDMAEN SPI RX DMA Enable This bit enables the SPI RX operating by through PDMA transfer RX data are saved in XRAM after SPI RX operation 0 SPI RX DMA Disabled 1 SPI RX DMA Enabled 1 0 SPIS 1 0 SP...

Страница 271: ...d an SPI interrupt will be required This bit should be cleared via software 4 MODF Mode Fault Error Flag This bit indicates a Mode Fault error event If SS pin is configured as Mode Fault input MSTR 1...

Страница 272: ...SPI1DR FCH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 SPInDR 7 0 R W Bit Name Description 7 0 SPInDR 7 0 Serial Peripheral Data This byte is used for transmitting or receiving data on SPI bus A write of this...

Страница 273: ...AAH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 MTMDA 7 4 XRAMA 7 4 R W R W Bit Name Description 7 4 MTMDA 7 4 Memory to Memory Destination Address High Byte The most significant 4 bits of XRAM address are us...

Страница 274: ...imer 2 interrupt priority high bit 6 PSPI0H SPI0 interrupt priority high bit 5 PFBH Fault Brake interrupt priority high bit 4 PWDTH WDT interrupt priority high bit 3 PPWM0H PWM0 interrupt priority hig...

Страница 275: ...SM2_1 Multiprocessor Communication Mode Enable The function of this bit is dependent on the serial port 1 mode Mode 0 No effect Mode 1 This bit checks valid stop bit 0 Reception is always valid no ma...

Страница 276: ...serial port 1 after the 8th bit in Mode 0 or the last data bit in other modes When the serial port 1 interrupt is enabled setting this bit causes the CPU to execute the serial port 1 interrupt servic...

Страница 277: ...ved 2 PDT45EN PWM4 5 Pair Dead Time Insertion Enable This bit is valid only when PWM4 5 is under complementary mode 0 No delay on GP4 GP5 pair signals 1 Insert dead time delay on the rising edge of GP...

Страница 278: ...BIAS 1 0 LCD Bias 00 Reserved 01 1 2 bias 10 1 3 bias 11 1 4 bias 3 2 DUTY 1 0 LCD Duty 00 1 4 duty 01 1 6 duty 10 1 8 duty 11 Reserved Note that when 1 4 duty is selected only COM0 to COM3 are used...

Страница 279: ...FAH Page 1 TA protected 0000_0000 b 7 6 5 4 3 2 1 0 PWM0DTCNT 7 0 R W Bit Name Description 7 0 PWM0DTCNT 7 0 PWM Dead Time Counter Low Byte This 8 bit field combined with PWMnDTEN 4 forms a 9 bit PWM...

Страница 280: ...S DISP LCDDIV 2 0 R W R W R W Bit Name Description 7 5 Reserved 4 LCDCKS LCD Clock Source Select 0 LIRC 24 1 LXT 24 3 DISP DISP The LCD display keeps display on or display off during chip power down m...

Страница 281: ...5 Register SFR Address Reset Value PWM0MEN FBH Page 1 0000_0000 b PWM1MEN 8DH Page 2 0000_0000 b PWM2MEN BDH Page 2 0000_0000 b PWM3MEN CDH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 PMEN5 PMEN4 PMEN3 PMEN2...

Страница 282: ...H Page 3 0000_0000 b 7 6 5 4 3 2 1 0 LCDPTR 4 0 R W Bit Name Description 7 5 Reserved 4 0 LCDPTR 4 0 LCD Data Pointer This field determines which LCD display data register is accessed by LCDDAT User s...

Страница 283: ...0_0000 b PWM1MD 8CH Page 2 0000_0000 b PWM2MD BCH Page 2 0000_0000 b PWM3MD CCH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 PMD5 PMD4 PMD3 PMD2 PMD1 PMD0 R W R W R W R W R W R W Bit Name Description 7 6 0 Rese...

Страница 284: ...CD Data Register SFR Address Reset Value LCDDAT FCH Page 3 0000_0000 b 7 6 5 4 3 2 1 0 LCDDAT 7 0 R W Bit Name Description 7 0 LCDDAT 7 0 LCD Data The value written into this register will be displaye...

Страница 285: ...l LVRFLTEN LVR Filter Enable TA Protected Register SFR Address Reset Value LVRFLTEN FDH Page 1 TA protected 0000_0000 b 7 6 5 4 3 2 1 0 LVRFLTEN 7 0 W Address FDH Page 1 reset value 0000 0000b Bit Nam...

Страница 286: ...Register SFR Address Reset Value LCDPWR FDH Page 3 0000_0000 b 7 6 5 4 3 2 1 0 PWR_SAVING 1 0 R W Bit Name Description 7 2 Reserved 1 0 PWR_SAVING 1 0 LCD_PWR_SAVING LCD driving cycle select turn on...

Страница 287: ...Name Description 7 PSPI1 SPI1 interrupt priority low bit 6 PDMA1 PDMA1 interrupt priority low bit 5 PDMA0 PDMA0 interrupt priority low bit 4 PSMC SMC interrupt priority low bit 3 PHF Hard fault interr...

Страница 288: ...LCD Blink Register SFR Address Reset Value LCDBL FEH Page 3 0000_0000 b 7 6 5 4 3 2 1 0 BLINK BLF 2 0 R W R W Bit Name Description 7 4 Reserved 3 BLINK LCD BLINK 0 LCD always on 1 LCD blink 2 0 BLF 2...

Страница 289: ...ame Description 7 PSPI1H SPI1 interrupt priority high bit 6 PDMA1H PDMA1 interrupt priority high bit 5 PDMA0H PDMA0 interrupt priority high bit 4 PSMCH SMC interrupt priority high bit 3 PHFH Hard faul...

Страница 290: ...CE MANUAL LVRDIS LVR Disable TA Protected Register SFR Address Reset Value LVRDIS FFH Page 0 TA protected 0000_0000 b 7 6 5 4 3 2 1 0 LVRDIS 7 0 W Bit Name Description 7 0 LVRDIS 7 0 LVR Disable To fi...

Страница 291: ...0000_0000 b 7 6 5 4 3 2 1 0 R_MODE BUF_EN VLCD_MODE 1 0 R W R W R W Bit Name Description 7 R_MODE Resister Mode 0 LCD none resister mode 1 LCD resister mode 6 BUF_EN Buffer Enable 0 buffer off 1 buff...

Страница 292: ...ls 38 4 kHz Internal Oscillator Flash Memory FHIRC FLIRC Clock Divider FSYS Watchdog Timer CKDIV Clock Filter CLO CLOEN CKCON 1 FLXT 4 24 MHz Oscillating Circuit FHXT FECLK 10X 01X 00X Self Wake up Ti...

Страница 293: ...sonator LXT and the external clock input ECLK through XIN pin User can set OSC 2 0 as 0 1 x to select ECLK as the system clock By setting OSC 2 0 as 1 1 0 HXT will be selected as the system clock By s...

Страница 294: ...ly by controlling CKSWT and CKEN registers via software It provides a wide flexibility in application Note that these SFR are writing TA protected for precaution With this clock source control the clo...

Страница 295: ...es to switch the system clock source to a disabled one by changing OSC 2 0 value OSC 2 0 value will be updated right away But the system clock will remain the original one and CKSWTF flag will be set...

Страница 296: ...illator is not stable or disabled 1 High speed internal oscillator is enabled and stable 4 LIRCST Low Speed Internal Oscillator 38 4 R W Status 0 Low speed internal oscillator is not stable or is disa...

Страница 297: ...d internal oscillator Enabled Note that once IAP is enabled by setting IAPEN CHPCON 0 the high speed internal 24 R W oscillator will be enabled automatically The hardware will also set HIRCEN and HIRC...

Страница 298: ...he MCU at a lower rate reducing power consumption By dividing the clock the MCU can retain the ability to respond to events other than those that can cause interrupts i e events that allow exiting the...

Страница 299: ...k frequency FSYS follows the equation below according to CKDIV value OSC SYS F F while CKDIV 00H and CKDIV 2 F F OSC SYS while CKDIV 01H to FFH System Clock Output 6 2 1 6 The ML51 ML54 ML56 Series pr...

Страница 300: ...CKCON 8EH Page 0 1000_0000b 7 6 5 4 3 2 1 0 FASTWK PWMCKS T1OE T1M T0M T0OE CLOEN R W R W R W R W R W R W R W Address 8EH Page 0 Reset value 1000 0000b Bit Name Description 1 CLOEN System Clock Outpu...

Страница 301: ...ctional mode Mode Clock Source Comment Normal mode Any clock source Idle mode Any clock source Only CPU clock is stoped Low power run mode Only for LIRC or LXT Low power idle mode Only for LIRC or LXT...

Страница 302: ...ogram continue executing the ISR of the very interrupt source that woke the system up before After return from the ISR the device continues execution at the instruction which follows the instruction t...

Страница 303: ...ll be the last instruction to be executed before the device enters Power down mode In the Power down mode RAM maintains its content The port pins output the values held by their own state before Power...

Страница 304: ...reset mode when VDD is lower than the voltage reference thresholds This design makes CPU not access program Flash while the VDD is not adequate performing the Flash reading If an undetermined operati...

Страница 305: ...00b Others 000U _0000b 7 6 5 4 3 2 1 0 SMOD SMOD0 LPR POF GF1 GF0 PD IDL R W R W RW R W R W R W R W R W Address 87H All pagess POR reset value 0001 000b other reset value 000U 0000b Bit Name Descripti...

Страница 306: ...suming event occurrence If the BORST bit is set as 1 this will enable brown out reset function After a brown out reset BORF BODCON0 1 will be set as 1 via hardware It will not be altered by reset othe...

Страница 307: ...lect 111 VBOD is 1 8V 110 VBOD is 1 8V 101 VBOD is 2 0V 100 VBOD is 2 4V 011 VBOD is 2 7V 010 VBOD is 3 0V 001 VBOD is 3 7V 000 VBOD is 4 4V 3 BOIAP Brown Out Inhibiting IAP This bit decides whether I...

Страница 308: ...4V 3 BOF Brown Out Interrupt Flag This flag will be set as logic 1 via hardware after a VDD dropping below or rising above VBOD event occurs If both EBOD I E 5 and EA I E 7 are set a brown out interr...

Страница 309: ...REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual Bit Name Description Note 1 BODEN BOV 2 0 and BORST are initialized by being directly loaded from CONFIG2 bit 7 6 4 and 2 after all re...

Страница 310: ...ry 1 6 ms periodically 10 BOD low power mode 2 by turning on BOD circuit every 6 4 ms periodically 11 BOD low power mode 3 by turning on BOD circuit every 25 6 ms periodically 0 BODFLT BOD Filter Cont...

Страница 311: ...g from address 0000H If an external reset applies while CPU is in Power down mode the way to trigger a hardware reset is slightly different Since the Power down mode stops system clock the reset signa...

Страница 312: ...DPS R W R W R W R W R W R R W Bit Name Description 6 RSTPINF External Reset Flag When the MCU is reset by the external reset this bit will be set via hardware It is recommended that the flag be cleare...

Страница 313: ...cated internal clock source User can clear the WDT at any time causing it to restart the counter When the selected time out occurs but no software response taking place for a while the WDT will reset...

Страница 314: ...tected POR 0000_0111 b WDT 0000_1UUU b Others 0000_UUUU b 7 6 5 4 3 2 1 0 WDTR WDCLR WDTF WIDPD WDTRF WDPS 2 0 R W R W R W R W R W R W Address AAH Page 0 Reset value POR 0000 0111b WDT 0000 1UUUb Othe...

Страница 315: ...mple if an ISP of Boot Code updating User Code finishes a software reset can be asserted to re boot CPU to execute new User Code immediately Writing 1 to SWRST CHPCON 7 will trigger a software reset N...

Страница 316: ...cted Register SFR Address Reset Value CHPCON 9FH Page 0 TA protected Software 0000_00U0 b Others 0000_00C0 b 7 6 5 4 3 2 1 0 SWRST IAPFF BS IAPEN W R W R W R W Bit Name Description 7 SWRST Software Re...

Страница 317: ...ESET pin U100 0000b Hard fault UU10 0000b Others UUU0 0000b 7 6 5 4 3 2 1 0 SWRF RSTPINF HardF HardFInt GF2 0 DPS R W R W R W R W R W R R W Bit Name Description 7 SWRF Software Reset Flag When the MCU...

Страница 318: ...BS 1 Hard fault reset Power on reset Figure 6 2 3 Boot Selecting Diagram The ML51 ML54 ML56 Series provides user a flexible boot selection for variant application The SFR bit BS in CHPCON 1 determines...

Страница 319: ...7 6 5 4 3 2 1 0 CBS FSYS OCDPWM OCDEN LOCK R W R W R W R W R W Factory default value 1111 1111b Bit Name Description 7 CBS CONFIG Boot Select This bit defines from which block that MCU re boots after...

Страница 320: ...unchanged after software reset After the MCU is released from reset state the hardware will always check the BS bit instead of the CBS bit to determine from which block that the device reboots Reset...

Страница 321: ...be terminated by a return from interrupt instruction RETI This instruction will force the CPU return to the instruction that would have been next when the interrupt occurred Source Vector Addess Vecto...

Страница 322: ...te that interrupts which occur when the EA bit is set to logic 0 will be held in a pending state and will not be serviced until the EA bit is set back to logic 1 All interrupt flags that generate inte...

Страница 323: ...rated ADCF ADCCON0 7 set 1 5 EBOD Enable Brown Out Interrupt 0 Brown out detection interrupt Disabled 1 Brown out detection interrupt Enable When interrupt generated BOF BODCON0 3 set 1 4 ES Enable Se...

Страница 324: ...ble Fault Brake Interrupt 0 Fault Brake interrupt Disabled 1 Fault Brake interrupt Enable When interrupt generated FBF PWM0FBD 7 set 1 4 EWDT Enable WDT Interrupt 0 WDT interrupt Disabled 1 WDT interr...

Страница 325: ...t generated SI R W1CON 3 or I2TOF R W1TOC 0 set 1 4 ESPI1 Enable SPI1 Interrupt 0 SPI1 interrupt Disabled 1 SPI1 interrupt Enable When interrupt generated SPIF SP2SR 7 MODF SP2SR 4 or SPIOVF SP2SR 5 s...

Страница 326: ...ock guard time interrupt Disabled 1 Block guard time interrupt Enabled 2 TERRIEN Transfer Error Interrupt Enable Bit This field is used to enable transfer error interrupt The transfer error states is...

Страница 327: ...hers are reserved no periperal source selected Note 0001 0011 1010 peripheral devices to XRAM memory 0101 0111 1110 XRAM memory to peripheral devices 3 HIE PDMA HALFTransfer Done Interrupt Enable Bit...

Страница 328: ...w priority interrupt handler will be invoked only if no other interrupt is already executing Again the low priority interrupt cannot preempt another low priority interrupt even if the later one is hig...

Страница 329: ...14 PT2 PT2H No Input capture 0063H CAPF0 CAPCON0 0 CAPF1 CAPCON0 1 CAPF2 CAPCON0 2 ECAP EIE0 2 15 PCAP PCAPH No PWM0 interrupt 006BH PWMF PWM0CON0 5 EPWM0 EIE0 3 16 PPWM0 PPWM0H No Serial port 1 007B...

Страница 330: ...SC1I E 4 28 SMC1 SMC1H No PDMA2 00E3H FDONE DMA2TSR 0 HDONE DMA2TSR 1 FIE DMA2CR0 2 HIE DMA2CR0 3 29 PDMA2 PDMA2H No PDMA3 00EBH FDONE DMA3TSR 0 HDONE DMA3TSR 1 FIE DMA3CR0 2 HIE DMA3CR0 3 30 PDMA3 PD...

Страница 331: ...Bit Name Description 7 Reserved 6 PADC ADC interrupt priority low bit 5 PBOD Brown out detection interrupt priority low bit 4 PS Serial port 0 interrupt priority low bit 3 PT1 Timer 1 interrupt priori...

Страница 332: ...DCH PBODH PSH PT1H PX1H PT0H PX0H R W R W R W R W R W R W R W Bit Name Description 7 6 PADCH ADC interrupt priority high bit 5 PBODH Brown out detection interrupt priority high bit 4 PSH Serial port 0...

Страница 333: ...Name Description 7 PT2 Timer 2 interrupt priority low bit 6 PSPI0 SPI0 interrupt priority low bit 5 PFB Fault Brake interrupt priority low bit 4 PWDT WDT interrupt priority low bit 3 PPWM0 PWM interru...

Страница 334: ...imer 2 interrupt priority high bit 6 PSPI0H SPI0 interrupt priority high bit 5 PFBH Fault Brake interrupt priority high bit 4 PWDTH WDT interrupt priority high bit 3 PPWM0H PWM0 interrupt priority hig...

Страница 335: ...Name Description 7 PSPI1 SPI1 interrupt priority low bit 6 PDMA1 PDMA1 interrupt priority low bit 5 PDMA0 PDMA0 interrupt priority low bit 4 PSMC SMC interrupt priority low bit 3 PHF Hard fault interr...

Страница 336: ...SPI1 interrupt priority high bit 6 PDMA1H PDMA1 interrupt priority high bit 5 PDMA0H PDMA0 interrupt priority high bit 4 PSMCH SMC interrupt priority high bit 3 PHFH Hard fault interrupt priority hig...

Страница 337: ...W Bit Name Description 7 RTC RTC interrupt priority low bit 6 PDMA3 PDMA3 interrupt priority low bit 5 PDMA2 PDMA2 interrupt priority low bit 4 SMC1 SMC1 interrupt priority low bit 3 TK Touch Key inte...

Страница 338: ...H RTCH interrupt priority high bit 6 PDMA3H PDMA3H interrupt priority high bit 5 PDMA2H PDMA2H interrupt priority high bit 4 SMC1H SMC1H interrupt priority high bit 3 TKH Touch Key interrupt priority...

Страница 339: ...ded that the flag be cleared via software 6 RSTPINF External Reset Flag When the MCU is reset by the external reset this bit will be set via hardware It is recommended that the flag be cleared via sof...

Страница 340: ...ck User should take care that the status of the stack The processor does not notice anything if the stack contents are modified and will proceed with execution from the address put back into PC Note t...

Страница 341: ...is moment the CPU holds the Program Counter and the built in IAP automation takes over to control the internal charge pump for high voltage and the detail signal timing The erase and program time is i...

Страница 342: ...llowing condition is met 1 The accessing address is oversize 2 IAPCN command is invalid 3 IAP erases or programs updating un enabled block 4 IAP erasing or programming operates under VBOD while BOIAP...

Страница 343: ...xff80 0xffff is mapping to APROM memory 1 CPU memory address 0xff80 0xffff is mapping to SPROM memory 3 SPUEN SPROM Memory Space Updated Enable TA Protected 0 Inhibit erasing or programming SPRO R W b...

Страница 344: ...W Bit Name Description 7 6 IAPB 1 0 IAP Control This byte is used for IAP command For details see Figure 6 3 1 IAP Modes and Command Codes 5 FOEN This Byte is Used for IAP Command For details see Figu...

Страница 345: ...NCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual IAPAH IAP Address High Byte Register SFR Address Reset Value IAPAH A7H Page 0 0000 _0000 b 7 6 5 4 3 2 1 0 IAPA 15 8 R W Bit Name Descriptio...

Страница 346: ...L56 SERIES TECHNICAL REFERENCE MANUAL IAPAL IAP Address Low Byte Register SFR Address Reset Value IAPAL A6H Page 0 0000 _0000 b 7 6 5 4 3 2 1 0 IAPA 7 0 R W Bit Name Description 7 0 IAPA 7 0 IAP Addre...

Страница 347: ...dress Reset Value IAPFD AEH Page 0 0000 _0000 b 7 6 5 4 3 2 1 0 IAPFD 7 0 R W Bit Name Description 7 0 IAPFD 7 0 IAP Flash Data This byte contains Flash data which is read from or is going to be writt...

Страница 348: ...is bit as logic 1 After this instruction the CPU holds the Program Counter PC and the IAP hardware automation takes over to control the progress After IAP action completed the Program Counter continue...

Страница 349: ...out D 7 0 PID 96 bit Unique Code read x x 0 0 0100 A 15 0 0x0000 0x000B Data out D 7 0 UID 16 bit VBG read x x 0 0 0100 A 15 0 0x000C 0x000D Data out D 7 0 VBG 128 bit Die Record read x x 0 0 0100 A...

Страница 350: ...a out SPROM page erase 10 1 0 0010 0180H FFH SPROM byte program 10 1 0 0001 0180H 01FFH Data in SPROM byte read 10 0 0 0000 0180H 01FFH Data out SPROM Erase 1 0 1 0 0010 A 15 0 0x0180 FFH SPROM Progra...

Страница 351: ...uring IAP progress interrupts if enabled should be disabled temporally by clearing EA bit for implement limitation Do not attempt to erase or program to a page that the code is currently executing Thi...

Страница 352: ...to trigger IAP process MOV IAPCN BYTE_PROGRAM_AP Program 201h with 55h MOV IAPAH 02h MOV IAPAL 01h MOV IAPFD 55h MOV TA 0Aah MOV TA 55h ORL IAPTRG 00000001b MOV TA 0Aah MOV TA 55h ANL IAPUEN 11111110b...

Страница 353: ...te TA 0Xaa CHPCON is TA protected TA 0x55 CHPCON 0x01 IAPEN 0 disable IAP mode P0 Data_Flash 1 Read content of address 200h 1 while 1 In System Programming ISP 6 3 1 5 The Flash Memory supports both h...

Страница 354: ...e CONFIG2 is also updated to disable BOD reset User needs to configure CONFIG0 0x7F CONFIG1 0Xfe CONFIG2 0xFF PAGE_ERASE_AP EQU 00100010b BYTE_PROGRAM_AP EQU 00100001b BYTE_READ_AP EQU 00000000b ALL_E...

Страница 355: ...PUEN 00000001b APUEN 1 enable APROM update RET Disable_AP_Update MOV TA 0Aah MOV TA 55h ANL IAPUEN 11111110b APUEN 0 disable APROM update RET Enable_CONFIG_Update MOV TA 0Aah MOV TA 55h ORL IAPUEN 000...

Страница 356: ...FD A CALL Trigger_IAP INC DPTR INC IAPAL MOV A IAPAL CJNE A 14 Program_AP_Loop RET Program_AP_Verify MOV IAPCN BYTE_READ_AP MOV IAPAH 00h MOV IAPAL 00h MOV DPTR AP_code Program_AP_Verify_Loop CALL Tri...

Страница 357: ...ble BOD reset MOV R6 A temp data CALL Trigger_IAP RET Program_CONFIG_Verify MOV IAPCN BYTE_READ_CONFIG MOV IAPAH 00h MOV IAPAL 02h CALL Trigger_IAP MOV B R6 MOV A IAPFD CJNE A B Program_CONFIG_Verify_...

Страница 358: ...memory access The OCD system does not occupy any locations in the memory map and does not share any on chip peripherals When the OCDEN CONFIG0 4 is programmed as 0 and LOCK CONFIG0 1 remains un progr...

Страница 359: ...its Power down mode under debug mode HIRC keeps turning on The ML51 ML54 ML56 Series OCD system has another limitation that non intrusive commands cannot be executed at any time while the user s progr...

Страница 360: ...Tri state pins those are used as PWM outputs 0 PWM continues 4 OCDEN OCD Enable 1 OCD Disabled 0 OCD Enabled Note If MCU run in OCD debug mode and OCDEN 0 hard fault reset will disable Only HardF flag...

Страница 361: ...n PxS register Schmitt triggered input has better glitch suppression capability All I O pins also have bit controllable slew rate select ability via software The Register Description are PxSR By defau...

Страница 362: ...ore source current is needed for an output driving Port Pin Input Port Latch P N VDD Strong Figure 6 4 2 Push Pull Mode Structure Input Only Mode Input only mode provides true high impedance input pat...

Страница 363: ...port latch is given by logic 0 If the port latch is logic 1 it behaves as if in input only mode To be used as an output pin generally as R W lines an open drain pin should add an external pull high ty...

Страница 364: ...00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL Input and Output Data Control 6 4 1 2 These registers are I O input and output data buffers Reading gets the I O input data Writing forces the data...

Страница 365: ...1111_1111 b P1 90H All pages Bit addressable 1111_1111 b P2 A0H All pages Bit addressable 1111_1111 b P3 B0H All pages Bit addressable 1111_1111 b P4 D8H All pages Bit addressable 1111_1111 b P5 B1H...

Страница 366: ...HNICAL REFERENCE MANUAL GPIO Mode Control 6 4 1 3 These registers control GPIO mode which is configurable among four modes input only quasi bidirectional push pull or open drain Each pin can be config...

Страница 367: ...er SFR Address Reset Value P0M1 B1H Page 1 1111_1111 b P1M1 B3H Page 1 1111_1111 b P2M1 85H Page 1 1111_1111 b P3M1 C2H Page 1 1111_1111 b P4M1 B9H Page 1 1111_1111 b P5M1 BDH Page 1 1111_1111 b P6M1...

Страница 368: ...1 0000_0000 b P3M2 C3H Page 1 0000_0000 b P4M2 BAH Page 1 0000_0000 b P5M2 BEH Page 1 0000_0000 b P6M2 85H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 PnM2_7 PnM2_6 PnM2_5 PnM2_4 PnM2_3 PnM2_2 PnM2_1 PnM2_0 R...

Страница 369: ...1 and Pn 0 Multi function Select Register SFR Address Reset Value P0MF10 F9H Page 2 0000_0000 b P1MF10 FDH Page 2 0000_0000 b P2MF10 F2H Page 2 0000_0000 b P3MF10 F6H Page 2 0000_0000 b P4MF10 EBH Pa...

Страница 370: ...SFR Address Reset Value P0MF32 FAH Page 2 0000_0000 b P1MF32 FEH Page 2 0000_0000 b P2MF32 F3H Page 2 0000_0000 b P3MF32 F7H Page 2 0000_0000 b P4MF32 ECH Page 2 0000_0000 b P5MF32 E1H Page 2 0000_00...

Страница 371: ...function Select Register SFR Address Reset Value P0MF54 FBH Page 2 0000_0000 b P1MF54 FFH Page 2 0000_0000 b P2MF54 F4H Page 2 0000_0000 b P3MF54 E9H Page 2 0000_0000 b P4MF54 EDH Page 2 0000_0000 b...

Страница 372: ...0000_0000 b P2MF76 F5H Page 2 0000_0000 b P3MF76 EAH Page 2 0000_0000 b P4MF76 EEH Page 2 0000_0000 b P5MF76 E3H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 PnMF7 3 0 PnMF6 3 0 R W R W Bit Name Description 7...

Страница 373: ...6 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual Input Type 6 4 1 5 Each I O pin can be configured individually as TTL input or Schmitt triggered input Note that al...

Страница 374: ...99H Page 1 0000_0000 b P1S 9BH Page 1 0000_0000 b P2S 9DH Page 1 0000_0000 b P3S ACH Page 1 0000_0000 b P4S BBH Page 1 0000_0000 b P5S BFH Page 1 0000_0000 b 7 6 5 4 3 2 1 0 PnS 7 PnS 6 PnS 5 PnS 4 Pn...

Страница 375: ...l Reference Manual Output Slew Rate Control 6 4 1 6 Slew rate for each I O pin is configurable individually By default each pin is in normal slew rate mode User can set each control register bit to en...

Страница 376: ...EH Page 1 0000_0000 b P6SR 8EH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 PnSR 7 PnSR 6 PnSR 5 PnSR 4 PnSR 3 PnSR 2 PnSR 1 PnSR 0 R W R W R W R W R W R W R W R W Bit Name Description 7 0 PnSR 7 0 Pn x Slew Ra...

Страница 377: ...SFR Address Reset Value P0UP 92H Page 1 0000_0000 b P1UP 93H Page 1 0000_0000 b P2UP 94H Page 1 0000_0000 b P3UP 95H Page 1 0000_0000 b P4UP 96H Page 1 0000_0000 b P5UP 97H Page 1 0000_0000 b 7 6 5 4...

Страница 378: ...S TECHNICAL REFERENCE MANUAL Pull Down Resister Control 6 4 1 8 Pull down resister for each I O pin is configurable individually Even enabled the pull down resister only effect when GPIO setting as in...

Страница 379: ...t Value P0DW 8AH Page 1 0000_0000 b P1DW 8BH Page 1 0000_0000 b P2DW 8CH Page 1 0000_0000 b P3DW 8DH Page 1 0000_0000 b P4DW 8EH Page 1 0000_0000 b P5DW 8FH Page 1 0000_0000 b P6DW 8FH Page 2 0000_000...

Страница 380: ...e INT0 or INT1 inputs are sampled every system clock cycle If the sample is high in one cycle and low in the next then a high to low transition is detected and the interrupts request flag IE0 or IE1 w...

Страница 381: ...rupt service routine If IT1 0 low level trigger this flag follows the inverse of the INT1 input signal s logic level Software cannot control it 2 IT1 External Interrupt 1 Type Select This bit selects...

Страница 382: ...pin interrupt channel allow the interrupt service routine to poll on which channel on which the interrupt event occurs All flags in PIF register are set by hardware and should be cleared by software...

Страница 383: ...el 6 is triggered 0 Level triggered 1 Edge triggered 5 PIT5 Pin Interrupt Channel 5 Type Select This bit selects which type that pin interrupt channel 5 is triggered 0 Level triggered 1 Edge triggered...

Страница 384: ...of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL Bit Name Description 0 PIT0 Pin Interrupt Channel 0 Type Select This bit selects which type that pin interrupt channel 0 is triggered...

Страница 385: ...age 1 0000_0000 b 7 6 5 4 3 2 1 0 PINEN7 PINEN6 PINEN5 PINEN4 PINEN3 PINEN2 PINEN1 PINEN0 R W R W R W R W R W R W R W R W Bit Name Description 7 0 PINENn Pin Interrupt Channel n Negative Polarity Enab...

Страница 386: ...4 3 2 1 0 PIPEN7 PIPEN6 PIPEN5 PIPEN4 PIPEN3 PIPEN2 PIPEN1 PIPEN0 R W R W R W R W R W R W R W R W Bit Name Description 7 0 PIPENn Pin Interrupt Channel n Positive Polarity Enable This bit enables high...

Страница 387: ...R level R W edge R level R W edge R level R W edge R level R W edge R level R W edge R level R W edge R level R W edge Bit Name Description 7 0 PIFn Pin Interrupt Channel n Flag If the edge trigger is...

Страница 388: ...000_0000 b PIPS5 A6H Page 1 0000_0000 b PIPS6 A7H Page 1 0000_0000 b PIPS7 AFH Page 1 0000_0000 b 7 6 5 4 3 2 1 0 PSEL 2 0 BSEL 2 0 R W R W Bit Name Description 7 Reserved 6 4 PSEL 2 0 Pin Interrupt C...

Страница 389: ...mode the countering register increases on the falling edge of the external input pin T0 If the sampled value is high in one clock cycle and low in the next a valid 1 to 0 transition is recognized on...

Страница 390: ...TE TR0 TR1 FSYS INT0 INT1 pin 1 12 0 1 T0M T1M Figure 6 5 2 Timer Counters 0 and 1 in Mode 1 Mode 2 8 Bit Auto Reload Timer 6 5 2 3 In Mode 2 the Timer Counter is in auto reload mode In this mode TL0...

Страница 391: ...to 0 transition counter on pin T0 as determined by C T TMOD 2 TH0 is forced as a clock cycle counter and takes over the usage of TR1 and TF1 from Timer Counter 1 Mode 3 is used in case that an extra 8...

Страница 392: ...ML51 ML54 ML56 Sep 01 2020 Page 392 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL Register Description 6 5 2 5...

Страница 393: ...the external pin T1 5 M1 Timer 1 Mode Select M1 M0 Timer 1 Mode 0 0 Mode 0 13 bit Timer Counter 0 1 Mode 1 16 bit Timer Counter 1 0 Mode 2 8 bit Timer Counter with auto reload from TH1 1 1 Mode 3 Time...

Страница 394: ...is bit can be set or cleared by software 4 TR0 Timer 0 Run Control 0 Timer 0 Disabled Clearing this bit will halt Timer 0 and the current count will be preserved in TH0 and TL0 1 Timer 0 Enabled 3 IE1...

Страница 395: ...L56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual Bit Name Description 0 IT0 External Interrupt 0 Type Select This bit selects by which type that INT0 is triggered...

Страница 396: ...SERIES TECHNICAL REFERENCE MANUAL TL0 Timer 0 Low Byte Register SFR Address Reset Value TL0 8AH Page 0 0000_0000b 7 6 5 4 3 2 1 0 TL0 7 0 R W Bit Name Description 7 0 TL0 7 0 Timer 0 Low Byte The TL0...

Страница 397: ...MANUAL ML51 ML54 ML56 Series Technical Reference Manual TH0 Timer 0 High Byte Register SFR Address Reset Value TH0 8CH Page 0 0000_0000b 7 6 5 4 3 2 1 0 TH0 7 0 R W Bit Name Description 7 0 TH0 7 0 T...

Страница 398: ...SERIES TECHNICAL REFERENCE MANUAL TL1 Timer 1 Low Byte Register SFR Address Reset Value TL1 8BH Page 0 0000_0000b 7 6 5 4 3 2 1 0 TL1 7 0 R W Bit Name Description 7 0 TL1 7 0 Timer 1 Low Byte The TL1...

Страница 399: ...MANUAL ML51 ML54 ML56 Series Technical Reference Manual TH1 Timer 1 High Byte Register SFR Address Reset Value TH1 8DH Page 0 0000_0000b 7 6 5 4 3 2 1 0 TH1 7 0 R W Bit Name Description 7 0 TH1 7 0 T...

Страница 400: ...be enabled only when operating in its Timer mode 4 T1M Timer 1 Clock Mode Select 0 The clock source of Timer 1 is the system clock divided by 12 It maintains standard 8051 compatibility 1 The clock so...

Страница 401: ...k divider with 8 different scales for wide field application The clock is enabled when TR2 T2CON 2 is 1 and disabled when TR2 is 0 The following registers are related to Timer 2 function Block Diagram...

Страница 402: ...Timer 2 Interrupt Pre scalar FSYS RCMP2H T2DIV 2 0 T2MOD 6 4 RCMP2L TH2 TL2 00 01 10 11 CAPF0 CAPF1 CAPF2 LDEN 1 T2MOD 7 LDTS 1 0 T2MOD 1 0 TR2 T2CON 2 Timer 2 Module C0H C0L Noise Filter ENF0 CAPCON...

Страница 403: ...ure channels has their own independent edge detector but share the unique Timer 2 Each trigger edge detector is selected individually by setting corresponding bits in CAPCON1 It supports positive edge...

Страница 404: ...ML51 ML54 ML56 Sep 01 2020 Page 404 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL Register Description 6 5 3 5...

Страница 405: ...Enabled 5 CAPEN1 Input Capture 1 Enable 0 Input capture channel 1 Disabled 1 Input capture channel 1 Enabled 4 CAPEN0 Input Capture 0 Enable 0 Input capture channel 0 Disabled 1 Input capture channel...

Страница 406: ...W R W R W Address E2H Page 1 Reset value 0000 0000b Bit Name Description 7 6 Reserved 5 4 CAP2LS 1 0 Input Capture 2 Level Select 00 Falling edge 01 Rising edge 10 Either rising or falling edge 11 Re...

Страница 407: ...F0 R W R W R W Bit Name Description 6 ENF2 Enable Noise Filer on Input Capture 2 0 Noise filter on input capture channel 2 Disabled 1 Noise filter on input capture channel 2 Enabled 5 ENF1 Enable Nois...

Страница 408: ...ure Low Byte n 0 1 2 Register SFR Address Reset Value C0L E4H Page 1 0000_0000 b C1L E6H Page 1 0000_0000 b C2L EDH Page 1 0000_0000 b 7 6 5 4 3 2 1 0 CnL 7 0 R W Bit Name Description 7 0 CnL 7 0 Inpu...

Страница 409: ...erence Manual CnH Capture n High Byte n 1 2 3 Register SFR Address Reset Value C0H E5H Page 1 0000_0000 b C1H E7H Page 1 0000_0000 b C2H EEH Page 1 0000_0000 b 7 6 5 4 3 2 1 0 CnH 7 0 R W Bit Name Des...

Страница 410: ...s set as 1 and a reload is generated and causes the contents of the RH3 and RL3 registers to be reloaded into the internal 16 bit counter If ET3 EIE1 1 is set as 1 Timer 3 interrupt service routine wi...

Страница 411: ...t when Timer 3 overflows It is automatically cleared by hardware when the program executes the Timer 3 interrupt service routine This bit can be set or cleared by software 3 TR3 Timer 3 Run Control 0...

Страница 412: ...L56 SERIES TECHNICAL REFERENCE MANUAL RL3 Timer 3 Reload Low Byte Register SFR Address Reset Value RL3 C5H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 RL3 7 0 R W Bit Name Description 7 0 RL3 7 0 Timer 3 Reloa...

Страница 413: ...ENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual RH3 Timer 3 Reload High Byte Register SFR Address Reset Value RH3 C6H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 RH3 7 0 R W Bit Name Description 7...

Страница 414: ...ime Out Timing 1 0 0 0 0 1 1 1 66 ms 0 0 0 1 1 4 6 64 ms 0 0 1 0 1 8 13 31 ms 0 0 1 1 1 16 26 62 ms 0 1 0 0 1 32 53 25 ms 0 1 0 1 1 64 106 66 ms 0 1 1 0 1 128 213 12 ms 0 1 1 1 1 256 426 64 ms 1 0 0 0...

Страница 415: ...onitor This is important in real time control applications In case of some power glitches or electro magnetic interference CPU may begin to execute erroneous codes and operate in an unpredictable stat...

Страница 416: ...ML51 ML54 ML56 Sep 01 2020 Page 416 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL 6 6 3 Register Description...

Страница 417: ...value 1111 1111b Bit Name Description 7 4 WDTEN 3 0 WDT Enable This field configures the WDT behavior after MCU execution 1111 WDT is Disabled WDT can be used as a general purpose timer via software c...

Страница 418: ...different Writing 0 No effect 1 Clearing WDT counter Reading 0 WDT counter is completely cleared 1 WDT counter is not yet cleared 5 WDTF WDT Time Out Flag This bit indicates an overflow of WDT counte...

Страница 419: ...nsumption of Idle mode still keeps at a Ma level To further reducing the current consumption to uA level the CPU should stay in Power down mode when nothing needs to be served and has the ability of w...

Страница 420: ...ML51 ML54 ML56 Sep 01 2020 Page 420 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL LOOP ORL PCON 02H LJMP LOOP...

Страница 421: ...abled along with WKT configuration User should manually enable the selected clock source and waiting for stability to ensure a proper operation The WKT is implemented simply as a 16 bit auto reload up...

Страница 422: ...ML51 ML54 ML56 Sep 01 2020 Page 422 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL 6 7 3 Control Register...

Страница 423: ...WKT Overflow Flag This bit is set when WKT overflows If the WKT interrupt and the global interrupt are enabled setting this bit will make CPU execute WKT interrupt service routine This bit is not aut...

Страница 424: ...H Self Wake up Timer Reload High Byte Register SFR Address Reset Value RWKH BFH Page 2 0000 0000b 7 6 5 4 3 2 1 0 RWK 15 8 R W Bit Name Description 7 0 RWK 15 8 WKT Reload High Byte It holds the 16 bi...

Страница 425: ...nical Reference Manual RWKL Self Wake up Timer Reload Low Byte Register SFR Address Reset Value RWKL 86H Page 0 0000 0000b 7 6 5 4 3 2 1 0 RWK 7 0 R W Bit Name Description 7 0 RWK 7 0 WKT Reload Low B...

Страница 426: ...CAL REFERENCE MANUAL CWKH Self Wake up Timer Current Count Value High Byte Register SFR Address Reset Value CWKH BEH Page 2 0000 0000b 7 6 5 4 3 2 1 0 CWK 15 8 R W Bit Name Description 7 0 CWK 15 8 WK...

Страница 427: ...ML51 ML54 ML56 Series Technical Reference Manual CWKL Self Wake up Timer Current Count Value Low Byte Register SFR Address Reset Value CWKL 86H Page 1 0000 0000b 7 6 5 4 3 2 1 0 CWK 7 0 R Bit Name Des...

Страница 428: ...If the complementary mode is used a programmable dead time insertion is available to protect MOS turn on simultaneously The PWM waveform can be edge aligned or center aligned with variable interrupt p...

Страница 429: ...Brake output control PWMTYP PWM0CON1 4 edge center Interrupt select type PWMDIV0 2 0 PWM0CON1 2 0 P0G0 PWM0 interrupt Brake event PWM0_BRAKE 0 1 Timer 1 overflow PWMCKS CKCON 6 FPWM Counter Matching...

Страница 430: ...WMnCON0 6 PWMF PWMnCON0 5 PWMnP buffer PWMnC0 buffer PWMnC0 Register 0 to 1 PWMn and Fault Brake output control PWMTYP PWMnCON1 4 edge center Interrupt select type PWMDIV0 2 0 PWMnCON1 2 0 PnG0 PWMn i...

Страница 431: ...duties of the PWM outputs In a three phase motor control application two group PWM outputs generally are given the same duty cycle When the group mode is enabled PWM0C2H PWM0C2L PWM0C3H PWM0C3L PWM0C4...

Страница 432: ...PWM0_CH0 PWM0_CH3 PWM0_CH1 PWM0_CH2 PWM0_CH5 PWM0_CH4 Figure 6 8 3 PWM0 and Fault Brake Output Control Block Diagram User should follow the initialization steps below to start generating the PWM signa...

Страница 433: ...PWMnCON1 7 6 Mask output PWMnMD0 PWMnMEN0 PWMnMD1 PWMnMEN1 PWMnC0 1 mode 0 1 0 1 PWMnMEN PWMnMD PWMn_CH0 PWMn_CH1 Figure 6 8 4 PWM1 2 3 Control Block Diagram Note A loading of new period and duty by...

Страница 434: ...OAD will be automatically cleared via hardware The meaning of writing and reading LOAD bit is different Writing 0 No effect 1 Load new period and duty in their buffers while a PWM period is completed...

Страница 435: ...ed on the next PWM cycle After the loading is complete LOAD will be automatically cleared via hardware The meaning of writing and reading LOAD bit is different Writing 0 No effect 1 Load new period an...

Страница 436: ...H Page 1 0000_0000 b PWM1CON1 9DH Page 2 0000_0000 b PWM2CON1 C5H Page 2 0000_0000 b PWM3CON1 D5H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 PWMMOD 1 0 GP PWMTYP FBINEN PWMDIV 2 0 R W R W R W R W R W Bit Name...

Страница 437: ...ference Manual CKCON Clock Control Register SFR Address Reset Value CKCON 8EH Page 0 0000_0000b 7 6 5 4 3 2 1 0 FASTWK PWMCKS T1OE T1M T0M T0OE CLOEN R W R W R W R W R W R W R W Bit Name Description 6...

Страница 438: ...Low Byte Register SFR Address Reset Value PWM0PL D9H Page 1 0000_0000 b PWM1PL 99H Page 2 0000_0000 b PWM2PL C1H Page 2 0000_0000 b PWM3PL D1H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 PWMnP 7 0 R W Bit Nam...

Страница 439: ...anual PWMnPH PWM Period High Byte Register SFR Address Reset Value PWM0PH D1H Page 1 0000_0000 b PWM1PH 86H Page 2 0000_0000 b PWM2PH B9H Page 2 0000_0000 b PWM3PH C9H Page 2 0000_0000 b 7 6 5 4 3 2 1...

Страница 440: ...High Byte This byte with PWMnCxL controls the duty of the output signal PGx from PWM generator Register SFR Address Reset Value PWM0C0H D2H Page 1 0000_0000 b PWM0C1H D3H Page 1 0000_0000 b PWM0C2H D4...

Страница 441: ...0 1 2 3 4 5 PWMnCx Duty Low Byte This byte with PWMnCxH controls the duty of the output signal PGx from PWM generator Register SFR Address Reset Value PWM0C0L DAH Page 1 0000_0000 b PWM0C1L DBH Page 1...

Страница 442: ...ep 01 2020 Page 442 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL PWM Types 6 8 4 2 The PWM generator provides two PWM types edge aligned or center aligned PWM type is selected by P...

Страница 443: ...al PWMnCON1 PWM Control 1 Register SFR Address Reset Value PWM0CON1 DFH Page 1 0000_0000 b PWM1CON1 9DH Page 2 0000_0000 b PWM2CON1 C5H Page 2 0000_0000 b PWM3CON1 D5H Page 2 0000_0000 b 7 6 5 4 3 2 1...

Страница 444: ...PWMnCH01 2nd Load PWMnP 2nd PWMnCH01 2nd duty valid PWMnP 2nd period valid 12 bit counter Figure 6 8 5 PWM Edge aligned Type Waveform The output frequency and duty cycle for edge aligned PWM are given...

Страница 445: ...tput frequency and duty cycle for center aligned PWM are given by following equations PWM frequency 2 PWMnPL PWMnPH FPWM FPWM is the PWM clock source frequency divided by PWMDIV PWM high level duty PW...

Страница 446: ...ignore PG1 3 5 Duty register PWMnH PWMnL n 1 3 5 This mode makes PG0 PG1 a PWM complementary pair and so on PG2 PG3 and PG4 PG5 In a real motor application a complementary PWM output always has a nee...

Страница 447: ...ep 01 2020 Page 447 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual PG0 PG1 PG0_DT PG1_DT Figure 6 8 7 PWM Complementary Mode with Dea...

Страница 448: ...Time Insertion Enable This bit is valid only when PWM4 5 is under complementary mode 0 No delay on GP4 GP5 pair signals 1 Insert dead time delay on the rising edge of GP4 GP5 pair signals 1 PDT23EN PW...

Страница 449: ...0 PWM Dead Time Counter Low Byte This 8 bit field combined with PWMnDTEN 4 forms a 9 bit PWM dead time counter PWM0DTCNT This counter is valid only when PWM is under complementary mode and the corres...

Страница 450: ...output function is quite useful when controlling Electrical Commutation Motor like a BLDC PWMnMEN contains six bits those determine which channel of PWM signal will be masked PWMnMD set the individual...

Страница 451: ...5 Register SFR Address Reset Value PWM0MEN FBH Page 1 0000_0000 b PWM1MEN 8DH Page 2 0000_0000 b PWM2MEN BDH Page 2 0000_0000 b PWM3MEN CDH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 PMEN5 PMEN4 PMEN3 PMEN2...

Страница 452: ...EN PWMnCON1 3 is set When Fault Brake is asserted PWM signals will be individually overwritten by PWMnFBD corresponding bits PWMRUN PWMnCON0 7 will also be automatically cleared by hardware to stop PW...

Страница 453: ...L51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual FBINEN FBn ADC comparator ADC compare event Fault Brake event De bounce 0 1 FBINLS FBF Fault Brake inte...

Страница 454: ...2 1 0 PWMMOD 1 0 GP PWMTYP FBINEN PWMDIV 2 0 R W R W R W R W R W Bit Name Description 3 FBINEN FB Pin Input Enable 0 PWM0 output Fault Braked by FB pin input Disabled 1 PWM0 output Fault Braked by FB...

Страница 455: ...is cleared Fault Brake data output will not be released until PWM0RUN PWM0CON0 7 is set 6 FBINLS PWM_BRAKE Pin Input Level Selection 0 Falling edge 1 Rising edge 5 0 FBDn PWMn Fault Brake Data 0 PWMn...

Страница 456: ...PWMn Negative Polarity Output Enable 0 PWMn signal outputs directly on PWMn pin 1 PWMn signal outputs inversely on PWMn pin 6 8 5 PWM Interrupt The PWM module has a flag PWMF PWMnCON0 5 to indicate c...

Страница 457: ...Reserved 5 4 INTTYP 1 0 PWM Interrupt Type Select These bit select PWM interrupt type 00 Falling edge on PWMn_CH0 1 2 3 4 5 pin 01 Rising edge on PWMn_CH0 1 2 3 4 5 pin 10 Central point of a PWM perio...

Страница 458: ...PWM counter Dead time PWMF falling edge INTTYP 1 0 0 0 PWMF rising edge INTTYP 1 0 0 1 Edge aligned PWM Center aligned PWM Reserved Figure 6 8 9 PWM Interrupt Type Fault Brake event requests another...

Страница 459: ...ML51 ML54 ML56 Sep 01 2020 Page 459 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual 6 8 6 Register Description...

Страница 460: ...OAD will be automatically cleared via hardware The meaning of writing and reading LOAD bit is different Writing 0 No effect 1 Load new period and duty in their buffers while a PWM period is completed...

Страница 461: ...ed on the next PWM cycle After the loading is complete LOAD will be automatically cleared via hardware The meaning of writing and reading LOAD bit is different Writing 0 No effect 1 Load new period an...

Страница 462: ...up Mode Enable This bit enables the group mode If enabled the duty of first three pairs of PWM are decided by PWM01H and PWM01L rather than their original duty Register Description 0 Group mode Disabl...

Страница 463: ...L56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual Bit Name Description 2 0 PWMDIV 2 0 PWM Clock Divider This field decides the pre scale of PWM clock source 000 1...

Страница 464: ...Low Byte Register SFR Address Reset Value PWM0PL D9H Page 1 0000_0000 b PWM1PL 99H Page 2 0000_0000 b PWM2PL C1H Page 2 0000_0000 b PWM3PL D1H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 PWMnP 7 0 R W Bit Nam...

Страница 465: ...anual PWMnPH PWM Period High Byte Register SFR Address Reset Value PWM0PH D1H Page 1 0000_0000 b PWM1PH 86H Page 2 0000_0000 b PWM2PH B9H Page 2 0000_0000 b PWM3PH C9H Page 2 0000_0000 b 7 6 5 4 3 2 1...

Страница 466: ...High Byte This byte with PWMnCxL controls the duty of the output signal PGx from PWM generator Register SFR Address Reset Value PWM0C0H D2H Page 1 0000_0000 b PWM0C1H D3H Page 1 0000_0000 b PWM0C2H D4...

Страница 467: ...0 1 2 3 4 5 PWMnCx Duty Low Byte This byte with PWMnCxH controls the duty of the output signal PGx from PWM generator Register SFR Address Reset Value PWM0C0L DAH Page 1 0000_0000 b PWM0C1L DBH Page 1...

Страница 468: ...Time Insertion Enable This bit is valid only when PWM4 5 is under complementary mode 0 No delay on GP4 GP5 pair signals 1 Insert dead time delay on the rising edge of GP4 GP5 pair signals 1 PDT23EN PW...

Страница 469: ...FAH Page 1 TA protected 0000_0000 b 7 6 5 4 3 2 1 0 PWM0DTCNT 7 0 R W Bit Name Description 7 0 PWM0DTCNT 7 0 PWM Dead Time Counter Low Byte This 8 bit field combined with PWMnDTEN 4 forms a 9 bit PWM...

Страница 470: ...Reset Value PWM0MEN FBH Page 1 0000_0000 b PWM1MEN 8DH Page 2 0000_0000 b PWM2MEN BDH Page 2 0000_0000 b PWM3MEN CDH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 PMEN5 PMEN4 PMEN3 PMEN2 PMEN1 PMEN0 R W R W R W...

Страница 471: ...0_0000 b PWM1MD 8CH Page 2 0000_0000 b PWM2MD BCH Page 2 0000_0000 b PWM3MD CCH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 PMD5 PMD4 PMD3 PMD2 PMD1 PMD0 R W R W R W R W R W R W Bit Name Description 7 6 0 Rese...

Страница 472: ...cription 7 FBF Fault Brake Flag This flag is set when FBINEN is set as 1 and FB pin detects an edge which matches FBINLS PWM0FBD 6 selection This bit is cleared by software After FBF is cleared Fault...

Страница 473: ...Reference Manual PWM0NP PWM Negative Polarity Register SFR Address Reset Value PWM0NP D6H Page 1 0000_0000 b 7 6 5 4 3 2 1 0 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0 R W R W R W R W R W R W Bit Name Description...

Страница 474: ...WM Interrupt Type Select These bit select PWM interrupt type 00 Falling edge on PWMn_CH0 1 2 3 4 5 pin 01 Rising edge on PWMn_CH0 1 2 3 4 5 pin 10 Central point of a PWM period 11 End point of a PWM p...

Страница 475: ...ceiver and Transmitter Mode 1 2 and 3 This means it can transmit and receive simultaneously The serial port is also receiving buffered meaning it can commence reception of a second byte before a previ...

Страница 476: ...troller bit by bit for a serial communication Data bits enter or emit LSB first The band rate is equal to the shift clock frequency Transmission is initiated by any instruction writes to SBUF The cont...

Страница 477: ...r the received stop bit 1 while SM2 1 and the received data matches Given or Broadcast address For enhancement function see Section 6 9 3 4 Multiprocessor Communication and Section 6 9 3 5 Automatic A...

Страница 478: ...B8 SCON 2 with the received 9 th bit and RI will be set If these conditions fail there will be no data loaded and RI will remain 0 After above receiving progress the serial control will look forward a...

Страница 479: ...1 SYS Time1 TM1 CKCON 3 1 TH1 256 F 32 1 SYS Timer 3 RL3 RH3 256 65536 scale Pre F 32 1 SYS 1 Time1 TM1 CKCON 3 0 TH1 256 12 F 16 1 SYS Time1 TM1 CKCON 3 1 TH1 256 F 16 1 SYS Timer 3 RL3 RH3 256 6553...

Страница 480: ...ort 1 Mode baud rate Description Sample code we list the most popular UART setting Mode 1 initial step as following Serial port 0 UART0 use timer 1 as baudrate generator Formula is TH1 256 F 16 1 SYS...

Страница 481: ...different Fsys and the deviation value Fsys Value Baud Rate TH1 Value Hex RH3 RL3 Value Hex Baudrate Deviation 24000000 4800 64 SMOD 0 FEC8 0 160256 9600 64 FF64 0 160256 19200 B2 FFB2 0 160256 38400...

Страница 482: ...067515 38400 E5 FFE5 0 067515 57600 EE FFEE 0 067515 115200 F7 FFF7 0 067515 16000000 4800 30 FF30 0 160256 9600 98 FF98 0 160256 19200 CC FFCC 0 160256 38400 E6 FFE6 0 160256 57600 EF FFEF 2 124183...

Страница 483: ...dentify the target slave Note that in this case an address byte differs from a data byte In an address byte the 9 th bit is 1 and in a data byte it is 0 The address byte interrupts all slaves so that...

Страница 484: ...g each of the slaves Use of the Given address allows multiple slaves to be recognized while excluding others The following examples will help to show the versatility of this scheme Example 1 slave 0 S...

Страница 485: ...dress 11100100b since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast address for each slave is created by taking the logical OR of SADDR and SADEN Zeros in this result are treated as...

Страница 486: ...ML51 ML54 ML56 Sep 01 2020 Page 486 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL 6 9 4 Register Description...

Страница 487: ...de 0 This bit select the baud rate between FSYS 12 and FSYS 2 0 The clock runs at FSYS 12 baud rate It maintains standard 8051compatibility 1 The clock runs at FSYS 2 baud rate for faster serial commu...

Страница 488: ...al port 0 after the 8th bit in Mode 0 or the last data bit in other modes When the serial port 0 interrupt is enabled setting this bit causes the CPU to execute the serial port 0 interrupt service rou...

Страница 489: ...SM2_1 Multiprocessor Communication Mode Enable The function of this bit is dependent on the serial port 1 mode Mode 0 No effect Mode 1 This bit checks valid stop bit 0 Reception is always valid no ma...

Страница 490: ...serial port 1 after the 8th bit in Mode 0 or the last data bit in other modes When the serial port 1 interrupt is enabled setting this bit causes the CPU to execute the serial port 1 interrupt servic...

Страница 491: ...0 SMOD SMOD0 LPR POF GF1 GF0 PD IDL R W R W RW R W R W R W R W R W Bit Name Description 7 SMOD Serial Port 0 Double Baud Rate Enable Setting this bit doubles the serial port baud rate when UART0 is i...

Страница 492: ...2 1 0 SMOD_1 SMOD0_1 BRCK TF3 TR3 T3PS 2 0 R W R W R W R W R W R W Bit Name Description 7 SMOD_1 Serial Port 1 Double Baud Rate Enable Setting this bit doubles the serial port baud rate when UART1 is...

Страница 493: ...b 7 6 5 4 3 2 1 0 SBUF 7 0 R W Bit Name Description 7 0 SBUF 7 0 Serial Port 0 Data Buffer This byte actually consists two separate registers One is the receiving resister and the other is the transm...

Страница 494: ...7 0 R W Bit Name Description 7 0 SBUF1 7 0 Serial Port 1 Data Buffer This byte actually consists two separate registers One is the receiving resister and the other is the transmitting buffer When data...

Страница 495: ...ual IE Interrupt Enable Bit addressable Register SFR Address Reset Value IE A8H All pages Bit addressable 0000 _0000 b 7 6 5 4 3 2 1 0 EA EADC EBOD ES ET1 EX1 ET0 EX0 R W R W R W R W R W R W R W R W B...

Страница 496: ...1 Register SFR Address Reset Value EIE1 9CH Page 0 0000 _0000 b 7 6 5 4 3 2 1 0 EPWM123 EI2C1 ESPI1 EHFI EWKT ET3 ES1 R W R W R W R W R W R W R W Bit Name Description 0 ES1 Enable Serial Port 1 Inter...

Страница 497: ...ML56 Series Technical Reference Manual SADDR0 Slave 0 Address Register SFR Address Reset Value SADDR0 A9H Page 0 0000 _0000 b 7 6 5 4 3 2 1 0 SADDR0 7 0 R W Bit Name Description 7 0 SADDR0 7 0 Slave...

Страница 498: ...R Address Reset Value SADEN0 B9H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 SADEN0 7 0 R W Bit Name Description 7 0 SADEN0 7 0 Slave 0 Address Mask This byte is a mask byte of UART0 that contains don t care b...

Страница 499: ...4 ML56 Series Technical Reference Manual SADDR1 Slave 1 Address Register SFR Address Reset Value SADDR1 BBH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 SADDR1 7 0 R W Bit Name Description 7 0 SADDR1 7 0 Slave...

Страница 500: ...R Address Reset Value SADEN1 BAH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 SADEN1 7 0 R W Bit Name Description 7 0 SADEN1 7 0 Slave 1 Address Mask This byte is a mask byte of UART1 that contains don t care b...

Страница 501: ...situation and no warning alarms 2 UART2PX Serial Port 2 RX SMC0 DATA TX SMC0 CLK Pin Exchange 0 Assign UART2 RXD SMC0 DATA to multiple I O pin RXD UART2 TXD SMC CLK to multiple I O pin TXD 1 Assign U...

Страница 502: ...I O pin RXD UART0 TXD to multiple I O pin TXD 1 Assign UART0 RXD to multiple I O pin TXD UART0 TXD to multiple I O pin RXD Note that Pin direction is controlled by I O type of relative pin RXD TXD wil...

Страница 503: ...0 T 1 compliant Programmable transmission clock frequency Programmable extra guard time selection Supports auto inverse convention function Supports UART mode Full duplex asynchronous communications S...

Страница 504: ...rol function to turn ON OFF the power for Smart Card Do not use SC_PWR as the direct power supply for Smart Card 6 SC_CD SC card detect pin input to MCU detect card by a card insert mechanism SC_CLK S...

Страница 505: ...igure 15 3 3 1 Set SC_RST to low by software programming to 0 before timing T4 2 Set SC_DAT to high by software programming to 1 period of timing T4 3 Set SC_RST to high by software programming to 1 a...

Страница 506: ...e 2 Fill 0 to CONSEL SCnCR1 4 and AUTOCEN SCnCR1 3 field In UART mode those fields must be 0 3 Select the UART baud rate by setting ETURDIV 11 0 SCnETURD1 3 0 SCnETURD0 7 0 fields For example if smart...

Страница 507: ...Inverse Convention Direct Convention t 12 9600ETU t 12 9600ETU D2 D3 D4 D5 D6 D7 D8 D1 D2 D3 D4 D5 D6 D7 D8 0_1101_1100_1 0x3B 0_1100_0000_1 0x3F Figure 6 10 4 Initial Character TS Error Signal and C...

Страница 508: ...Transmitter Data Figure 6 10 6 Transmit Direction Block Guard Time Operation In receive direction the smart card host controller sends data to smart card first If the smart card sends data to smart c...

Страница 509: ...ML51 ML54 ML56 Sep 01 2020 Page 509 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual 6 10 6 Register Description...

Страница 510: ...e bit length of block guard time According to ISO7816 3 in T 0 mode the software must clear T bit to 0 for real block guard time 16 5 In T 1 mode the software must set T bit to 1 for real block guard...

Страница 511: ...tion the setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F After hardware received first data and stored it at buffer hardware will decided the convention...

Страница 512: ...t data word bit and stop bit of the serial data 1 Parity bit is not generated transmitting data or checked receiving data during transfer Note In smart card mode this field must be 0 default setting i...

Страница 513: ...al Bit Name Description 0 UARTEN UART Mode Enable Bit 0 Smart Card mode 1 UART mode Note 1 When operating in UART mode user must set CONSEL SCnCR0 4 0 and AUTOCEN SCnCR0 3 0 Note 2 When operating in S...

Страница 514: ...0000_0000 b SC1DR D9H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 SCnDR 7 0 R W Bit Name Description 7 0 SCnDR 7 0 SC UART Buffer Data This byte is used for transmitting or receiving data on SC UART bus A writ...

Страница 515: ...Technical Reference Manual SCnEGT SC0 1 Extra Guard Time Register Register SFR Address Reset Value SC0EGT DAH Page 0 0000_0000 b SC1EGT DAH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 SCnEGT 7 0 R W Bit Name D...

Страница 516: ...ss Reset Value SC0ETURD0 DBH Page 0 0111_0011 b SC1ETURD0 DBH Page 2 0111_0011 b 7 6 5 4 3 2 1 0 ETURDIV 7 0 R W Bit Name Description 7 0 ETURDIV 7 0 LSB Bits of ETU Rate Divider The field indicates t...

Страница 517: ...W R W Bit Name Description 7 Reserved 6 4 SCDIV 2 0 SC Clock Divider 000 FSC is FSYS 1 001 FSC is FSYS 2 010 FSC is FSYS 4 011 FSC is FSYS 8 By default 100 FSC is FSYS 16 101 FSC is FSYS 16 110 FSC i...

Страница 518: ...ock guard time interrupt Disabled 1 Block guard time interrupt Enabled 2 TERRIEN Transfer Error Interrupt Enable Bit This field is used to enable transfer error interrupt The transfer error states is...

Страница 519: ...2 TERRIF Transfer Error Interrupt Status Flag Read Only This field is used for transfer error interrupt status flag The transfer error states is at SC0TSR register which includes receiver break error...

Страница 520: ...he received character does not have a valid stop bit that is the stop bit following the last data bit or parity bit is detected as logic 0 Note This bit is read only but it can be cleared by writing 0...

Страница 521: ...L56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual Bit Name Description 0 RXOV RX Overflow Error Status Flag Read Only This bit is set when RX buffer overflow Note...

Страница 522: ...gh speed synchronous communication bus between microcontrollers or other peripheral devices such as serial EEPROM LCD driver or D A converter It provides either Master or Slave mode high speed rate up...

Страница 523: ...ect MSB LSB Pin Contorl Logic MISO MOSI SPCLK SS SPI Status Control Logic SPI Status Register SPI Control Register Clock Logic S M M S CLOCK SPIF WCOL SPIOVF MODF DISMODF SPI Interrupt SPIEN MSTR MSTR...

Страница 524: ...k is driven by the Master mode device for eight clock cycles Eight clocks exchange one byte data on the serial lines For the shift clock is always produced out of the Master device the system should n...

Страница 525: ...e The SPI can operate in Master mode while MSTR SPInCR 4 is set as 1 Only one Master SPI device can initiate transmissions A transmission always begins by Master through writing to SPInDR The byte wri...

Страница 526: ...ve If SPI interrupt enable bit is set 1 and global interrupt is enabled EA 1 the interrupt service routine ISR of SPI will be executed Concerning the Slave mode the SS signal needs to be taken care As...

Страница 527: ...SSOE 1 SPCLK Cycles Figure 6 11 5 SPI Clock and Data Format with CPHA 0 Transfer Progress 1 internal signal SPCLK Cycles SPCLK CPOL 0 MOSI SS output of Master 2 SPIF Master 1 2 3 4 5 6 7 8 SPCLK CPOL...

Страница 528: ...SPInCR are cleared via hardware to disable SPI Mode Fault flag MODF SPInSR 4 is set and an interrupt is generated if ESPI and EA are enabled Write Collision Error The SPI is signal buffered in the tra...

Страница 529: ...will be set again 1 2 3 3 4 Figure 6 11 7 SPI Overrun Waveform SPI Interrupt 6 11 4 5 Three SPI status flags SPIF MODF and SPIOVF can generate an SPI event interrupt requests All of them locate in SP...

Страница 530: ...each transmission when selecting external Slave device and goes high during each idle state to de select the Slave device 6 SPIEN SPI Enable 0 SPI function Disabled 1 SPI function Enabled 5 LSBFE LSB...

Страница 531: ...SPI clock rate 0 0 0 0 2 12M bit s 0 0 0 1 4 6M bit s 0 0 1 0 8 3M bit s 0 0 1 1 16 1 5M bit s 0 1 0 0 32 750k bit s 0 1 0 1 64 375k bit s 0 1 1 0 128 187k bit s 0 1 1 1 256 93 7k bit s 1 0 0 0 3 8M b...

Страница 532: ...clock rates below are illustrated under FSYS 24 MHz condition SPR3 SPR2 SPR1 SPR0 Divider SPI clock rate 0 0 0 0 2 12M bit s 0 0 0 1 4 6M bit s 0 0 1 0 8 3M bit s 0 0 1 1 16 1 5M bit s 0 1 0 0 32 750...

Страница 533: ...bled 1 SPI TX DMA Enabled 2 RXDMAEN SPI RX DMA Enable This bit enables the SPI RX operating by through PDMA transfer RX data are saved in XRAM after SPI RX operation 0 SPI RX DMA Disabled 1 SPI RX DMA...

Страница 534: ...be required This bit should be cleared via software 4 MODF Mode Fault Error Flag This bit indicates a Mode Fault error event If SS pin is configured as Mode Fault input MSTR 1 and DISMODF 0 and SS is...

Страница 535: ...R F5H Page 0 0000_0000 b SPI1DR FCH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 SPInDR 7 0 R W Bit Name Description 7 0 SPInDR 7 0 Serial Peripheral Data This byte is used for transmitting or receiving data on...

Страница 536: ...ial mode General Call is also available The I 2 C can meet both standard up to 100kbps and fast up to 400k bps speeds 6 12 2 Features 2 sets of I 2 C devices Master Slave mode Bidirectional data trans...

Страница 537: ...the data receiving device can hold SCL line stretched low if next receiving is not prepared ready It forces the next byte transaction suspended The data transaction continues when the receiver releas...

Страница 538: ...e The master keeps transmitting data after the slave returns acknowledge to the master A acknowledge SDA low A not acknowledge SDA high S START condition P STOP condition 0 write S SLAVE ADDRESS R W A...

Страница 539: ...a STOP or a repeated START condition If a slave receiver does acknowledge the slave address it switches itself to not addressed slave mode and cannot receive any more data bytes This slave leaves the...

Страница 540: ...port hardware looks for its own slave address and the general call address If one of these addresses is detected and if the slave is willing to receive or transmit data from to master by setting the A...

Страница 541: ...T condition as soon as the bus becomes free After a START condition is successfully produced the SI flag I2CnCON 3 will be set and the status code in I2CnSTAT show 08H The progress is continued by loa...

Страница 542: ...STO SI AA 1 1 1 x I2CnDAT SLA W ACK NAK Arbitration Lost STATUS 0x38 I2C_DAT SLA W STA STO SI AA 0 0 1 x I2CnDAT Data ACK NAK STATUS 0x38 I2C_DAT Data STA STO SI AA 0 0 1 x Arbitration Lost STA STO S...

Страница 543: ...generate a STOP condition or a repeated START condition to terminate the transmission or initial another one I2CnDAT SLA R ACK NAK I2CnDAT Data NAK I2CnDAT Data ACK P S P Sr I2CnDAT SLA R STA STO SI...

Страница 544: ...and isolate with the master It cannot receive any byte of data with I2CnDAT remaining the previous byte of data which is just received Slave Transmitter The I 2 C port is equipped with four slave addr...

Страница 545: ...ta STA STO SI AA 0 0 1 0 STATUS 0xB8 Switch to not addressed mode Own SLA will be recognized ACK I2CnDAT Data I2CnDAT Data STA STO SI AA 0 0 1 0 NAK STATUS 0xC8 STATUS 0xC0 Arbitration Lost STATUS 0xB...

Страница 546: ...bus free S STA STO SI AA 1 0 1 0 Switch to not addressed mode Own SLA will not be recognized Send START when bus free Switch to not addressed mode Address 0x0 will be recognized STA STO SI AA 0 0 1 0...

Страница 547: ...ms the same action as above In this case state 08H is entered instead of 10H after a successful START condition is transmitted Note that the software is not involved in solving these bus problems The...

Страница 548: ...54 ML56 SERIES TECHNICAL REFERENCE MANUAL not set for a period The 14 bit time out counter will overflow and require the interrupt service 1 0 FSYS 1 4 14 bit I2 C Time out Counter I2TOF Clear Counter...

Страница 549: ...s Reset Value I2C0TOC BFH Page 0 0000_0000 b I2C1TOC B6H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 I2TOCEN DIV I2TOF R W R W R W Bit Name Description 7 3 Reserved 2 I2TOCEN I2C0 Time Out Counter Enable 0 I 2...

Страница 550: ...errupt service routine once any of these two flags is set User needs to check flags to determine what event caused the interrupt Both of I 2 C flags are cleared by software 6 12 6 Register Description...

Страница 551: ...ion following If STA is set while the I 2 C is already in the master mode and one or more bytes have been transmitted or received the I 2 C generates a repeated START condition Note that STA can be se...

Страница 552: ...K low level on SDA will be returned during the acknowledge clock pulse of the SCL line while the I 2 C device is a receiver or an own address matching slave If the AA flag is cleared a NACK high level...

Страница 553: ...I2CnSTAT 7 3 0 0 0 R R R R Bit Name Description 7 3 I2CnSTAT 7 3 I2Cn Status Code The MSB five bits of I2CnSTAT contains the status code There are 27 possible status codes When I2CnSTAT is F8H no rele...

Страница 554: ...as just received Data in I2CnDAT remains as long as SI is logic 1 The result of reading or writing I2CnDAT during I 2 C transceiver progress is unpredicted While data in I2CnDAT is shifted out data on...

Страница 555: ...Own Slave Address In master mode These bits have no effect In slave mode These 7 bits define the slave address of this I 2 C device by user The master should address I 2 C device by sending the same a...

Страница 556: ...R W Bit Name Description 7 0 I2CnCLK 7 0 I2Cn Clock Setting In master mode This register determines the clock rate of I2 C bus when the device is in a master mode The clock rate follows the equation 1...

Страница 557: ...tine can never be invoked Void I2C_ISR void interrupt 6 switch I2STAT Bus Error always put in ISR for noise handling case 0x00 00H bus error occurs STO 1 recover from bus error break Master Mode case...

Страница 558: ...ext received DATA else if continuing receiving DATA AA 1 break case 0x58 58H DATA received NACK transmitted DATA_RECEIVED_LAST1 I2DAT STO 1 AA 1 break Slave Receiver and General Call Mode case 0x60 60...

Страница 559: ...e entered DATA_RECEIVED_LAST3 I2DAT AA 1 break Slave Mode case 0Xa0 A0H STOP or repeated START received while still addressed SLAVE mode AA 1 break Slave Transmitter Mode case 0Xa8 A8H own SLA R recei...

Страница 560: ...MANUAL AA 1 break case 0Xc8 C8H previous own SLA R last DATA trans mitted ACK received not addressed SLAVE AA 1 mode entered break end of switch I2STAT SI 0 SI should be the last command of I2 C ISR w...

Страница 561: ...56 Series is selected as 8 channel inputs in single end mode The internal band gap voltage 0 814 V also can be the internal ADC input The analog input multiplexed into one sample and hold circuit char...

Страница 562: ...ADCRH ADCRL ADCF ADC result comparator External Trigger VDD ADCEN ADCS ADC XRAM Control ADCBAH ADCSN XRAM Auxiliary RAM ADC Interrupt 1 2 ADC flag Re trigger VREF V REF ADC VDD STADC ADC_CH0 ADC_CH1 A...

Страница 563: ...the hardware will clear ADCS automatically set ADCF ADCCON0 7 and generate an interrupt if enabled The new conversion result will also be stored in ADCRH most significant 8 bits and ADCRL least signi...

Страница 564: ...compare function the ADCF register changes to 1 only when ADC comparing result matches the condition and then enters interrupt vector if ADC interrupt is enabled After this bit is enabled and ADC sta...

Страница 565: ...11 0 N ADCBA 11 0 N 1 ADCBA 11 0 N 2 ADCBA 11 0 N N 2 ADC conversion result ADC Continues Conversion schedule XRAM Figure 6 13 4 ADC Continues mode with DMA A programing sequence is described below 1...

Страница 566: ...ML51 ML54 ML56 Sep 01 2020 Page 566 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL 6 13 4 Register Description...

Страница 567: ...ng hit if result comparator is enabled The ADC result can be read While this flag is 1 ADC cannot start a new converting This bit is cleared by software 6 ADCS A D Converting Software Start Trigger Se...

Страница 568: ...ed selects the activating analog input source of ADC If ADCEN is 0 all inputs are disconnected 0000 ADC_CH0 0001 ADC_CH1 0010 ADC_CH2 0011 ADC_CH3 0100 ADC_CH4 0101 ADC_CH5 0110 ADC_CH6 0111 ADC_CH7 1...

Страница 569: ...is set while total A D conversions are completed 3 2 ETGTYP 1 0 External Trigger Type Select When ADCEX ADCCON1 1 is set these bits select which condition triggers ADC conversion 00 Falling edge on PW...

Страница 570: ...C compare value defined ADCF will be set to 1 This condition base on ADCMPH ADCMPL and ADCMPOP register define The ADCF register changes to 1 only when ADC comparing result matches the condition and t...

Страница 571: ...W Bit Name Description 7 0 ADCDLY 7 0 ADC External Trigger Delay Counter Low Byte This 8 bit field combined with ADCCON2 0 forms a 9 bit counter This counter inserts a delay after detecting the extern...

Страница 572: ...FR Address Reset Value AINDIDS0 CEH Page 1 0000_0000 b 7 6 5 4 3 2 1 0 AIN7DIDS AIN6DIDS AIN5DIDS AIN4DIDS AIN3DIDS AIN2DIDS AIN1DIDS AIN0DIDS R W R W R W R W R W R W R W R W Bit Name Description 7 0...

Страница 573: ...Digital Input Disconnect Register SFR Address Reset Value AINDIDS1 CEH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 AIN15DIDS AIN14DIDS AIN13DIDS AIN12DIDS AIN11DIDS AIN10DIDS R W R W R W R W R W R W Bit Name D...

Страница 574: ...S TECHNICAL REFERENCE MANUAL ADCRH ADC Result High Byte Register SFR Address Reset Value ADCRH C3H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCR 11 4 R Bit Name Description 7 0 ADCR 11 4 ADC Result High Byt...

Страница 575: ...ML51 ML54 ML56 Series Technical Reference Manual ADCRL ADC Result Low Byte Register SFR Address Reset Value ADCRL C2H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCR 3 0 R Bit Name Description 7 4 Reserved 3...

Страница 576: ...ICAL REFERENCE MANUAL ADCMPH ADC Compare High Byte Register SFR Address Reset Value ADCMPH CFH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCMP 11 4 W R Bit Name Description 7 0 ADCMP 11 4 ADC Compare High By...

Страница 577: ...4 ML56 Series Technical Reference Manual ADCMPL ADC Compare Low Byte Register SFR Address Reset Value ADCMPL CEH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCMP 3 0 W R Bit Name Description 7 4 Reserved 3 0...

Страница 578: ...ddress High Byte Register SFR Address Reset Value ADCBAH E4H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCBA 3 0 R W Bit Name Description 7 4 Reserved 3 0 ADCBA 3 0 ADC RAM Base Address High Byte The most si...

Страница 579: ...RAM Base Address Low Byte Register SFR Address Reset Value ADCBAL CBH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCBA 7 0 R W Address CBH Page 0 Reset value 0000 0000b Bit Name Description 7 0 ADCBA 7 0 ADC...

Страница 580: ...REFERENCE MANUAL ADCSN ADC Sampling Number Register SFR Address Reset Value ADCSN E5H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCSN 7 0 R W Bit Name Description 7 0 ADCSN 7 0 ADC Sampling Number The total...

Страница 581: ...ies Technical Reference Manual ADCCN ADC Current Sampling Number Register SFR Address Reset Value ADCCN E6H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCCN 7 0 R Bit Name Description 7 0 ADCCN 7 0 ADC Curren...

Страница 582: ...010 FADC is FSYS 4 011 FADC is FSYS 8 100 FADC is FSYS 16 101 FADC is FSYS 32 110 FADC is FSYS 64 111 FADC is FSYS 128 3 Reserved 2 CMPHIT ADC Comparator Hit Flag This bit is set by hardware when ADC...

Страница 583: ...to AVSS Set pre load is to reduce stable time of VREF_IN At first enable VREF_IN and turn on pre load at the same time the minimum stable time of pre load on the VREF_IN must be greater than 3 ms Afte...

Страница 584: ...L 2 0 Internal VREF Output Voltage Select This field selects VREF output voltage 000 1 538V when VDD 2 0V 001 2 048V when VDD 2 4V 010 2 560V when VDD 2 9V 011 3 072V when VDD 3 4V 100 4 096V when VDD...

Страница 585: ...errupt when the comparator output value changes 6 15 2 Feature Analog input voltage range 0 AVDD voltage of AVDD pin Supports hysteresis function Supports wake up function Selectable input sources of...

Страница 586: ...3 ACMP_P0 P2 5 ACMP_P3 P3 1 ACMP_P2 P2 1 11 10 01 00 VBG ACMP1_N1 P3 2 ACMP1_N0 P2 2 NEGSEL ACMPCR1 5 4 ACMP1 ACMPEN ACMPCR1 0 11 10 01 00 POSSEL ACMPCR1 7 6 ACMP0IF ACMPSR 0 CRV1CTL 2 0 ACMPVREF 6 4...

Страница 587: ...e by a low threshold voltage High threshold voltage Low threshold voltage Positive input voltage Negative input voltage Comparator output Figure 6 15 2 Comparator Hysteresis Function Comparator Refere...

Страница 588: ...e 6 15 3 Comparator Reference Voltage Block Diagram Note that If CRVEN 0 CRV0 is equal to 0 and CRV1 is equal to Band gap Interrupt Sources 6 15 4 3 The comparator generates an output ACMPnO ACMPSR If...

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Страница 590: ...mparator 0 Negative Input Selection 00 ACMP0_N0 P2 4 pin 01 Internal comparator reference voltage CRV 10 VBG Band gap 11 ACMP0_N1 P2 0 pin 3 WKEN Comparator 0 Power Down Wake Up Enable Bit 0 Comparato...

Страница 591: ...3 P3 1 pin 5 4 NEGSEL Comparator 1 Negative Input Selection 00 ACMP1_N0 P2 2 pin 01 Internal comparator reference voltage CRV 10 VBG Band gap 11 ACMP1_N1 P3 2 pin 3 WKEN Comparator 1 Power Down Wake U...

Страница 592: ...s 10uA typ 11 fast speed propagation delay 0 2us 75uA typ 5 POE1 Analog Comparator 1 Polarity Output Enable 0 ACMP1 output directly 1 ACMP1 output inversely 4 POE0 Analog Comparator 0 Polarity Output...

Страница 593: ...ACMPEN ACMPCR1 0 is cleared to 0 Note This bit is read only 2 ACMP1IF Comparator 1 Interrupt Flag This bit is set by hardware whenever the comparator 1 output changes state This will generate an inter...

Страница 594: ...r Register SFR Address Reset Value ACMPVREF D5H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 CRV1CTL 2 0 CRV0CTL 2 0 R W R W Bit Name Description 7 Reserved 6 4 CRV1CTL 2 0 Comparator 1 Reference Voltage Settin...

Страница 595: ...ddress to another without CPU intervention This has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications 6 16 2 Feature Supports transfer data width of 8 bit...

Страница 596: ...ot in wrap around mode the PDMA will continue the transfer until DMAnCCNT counts down to 0 In wrap around mode when DMAnCCNT counts down to 0 the PDMA will reload DMAnCCNT and work around until user c...

Страница 597: ...eration stops until user clears the error condition and then clears the EN DMAnCR 0 bit to disable the PDMA channel then sets EN DMAnCR 0 bit and RUN DMAnCR 1 bit to start operation again Memory to Me...

Страница 598: ...f 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL CRC 8 Function for PDMA 6 16 4 2 Bit order Revise F F Data_in 7 0 Seed 7 0 CRC 7 0 CRC_active Bit order Revise REFIN REFOUT CRC 8 X8 X2...

Страница 599: ...ML51 ML54 ML56 Sep 01 2020 Page 599 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual 6 16 5 Register Description...

Страница 600: ...pheral source selected Note 0001 0011 1010 peripheral devices to XRAM memory 0101 0111 1110 XRAM memory to peripheral devices 3 HIE PDMA HALFTransfer Done Interrupt Enable Bit 0 Interrupt Disabled whe...

Страница 601: ...set Value DMA0MAL 93H Page 0 0000_0000 b DMA1MAL ECH Page 0 0000_0000 b DMA2MAL B4H Page 2 0000_0000 b DMA3MAL ACH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 MAL 7 0 R W Bit Name Description 7 0 MAL 7 0 PDMA...

Страница 602: ...Page 2 0000_0000 b 7 6 5 4 3 2 1 0 MTMDA 7 4 XRAMA 7 4 R W R W Bit Name Description 7 4 MTMDA 7 4 Memory to Memory Destination Address High Byte The most significant 4 bits of XRAM address are used f...

Страница 603: ...nCNT PDMA Transfer Count Register SFR Address Reset Value DMA0CNT 94H Page 0 0000_0000 b DMA1CNT EDH Page 0 0000_0000 b DMA2CNT B5H Page 2 0000_0000 b DMA3CNT ADH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 DM...

Страница 604: ...H Page 2 0000_0000 b DMA3CCNT AEH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 DMAnCCNT 7 0 R Bit Name Description 7 0 DMAnCCNT 7 0 PDMA Current Transfer Count The current transfer count for PDMA request operat...

Страница 605: ...7 6 5 4 3 2 1 0 ACT HDONE FDONE R R W R W Bit Name Description 7 3 Reserved 2 ACT PDMA in Active Status Flag Read Only 0 This bit is cleared automatically when PDMA transfer is done or disabled 1 This...

Страница 606: ...t Value MTM0DA EAH Page 0 0000_0000 b MTM1DA F2H Page 0 0000_0000 b MTM2DA B7H Page 2 0000_0000 b MTM3DA AFH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 MTMnDA 7 0 R W Bit Name Description 7 0 MTMnDA 7 0 Memor...

Страница 607: ...ble Bit 0 CRC OUT exclusive ored Disabled when PDMA is running 1 CRC OUT exclusive ored Enabled when PDMA is running the final value is exclusive ored with 0x55 2 REFOUT PDMA CRC OUT Reflect Enable Bi...

Страница 608: ...SFR Address Reset Value DMA0CRC 92H Page 3 0000_0000 b DMA1CRC 93H Page 3 0000_0000 b DMA2CRC 94H Page 3 0000_0000 b DMA3CRC 95H Page 3 0000_0000 b 7 6 5 4 3 2 1 0 CRC 7 0 R W Bit Name Description 7...

Страница 609: ...lue DMA0SEED 9AH Page 3 0000_0000 b DMA1SEED 9BH Page 3 0000_0000 b DMA2SEED 9CH Page 3 0000_0000 b DMA3SEED 9DH Page 3 0000_0000 b 7 6 5 4 3 2 1 0 SEED 7 0 R W Bit Name Description 7 0 SEED 7 0 PDMA...

Страница 610: ...or Type B The source of LCD clock is based on the choice of LIRC or LXT The LCD display can keep display on or off during chip in power down mode The LCD power supply VLCD source is selectable from in...

Страница 611: ...0 LCDCON0 5 4 LCDCKS LCDCLK 4 LCDDIV 2 0 LCDCLK 2 0 DISP LCDCLK 3 DUTY 1 0 LCDCON0 3 2 LCDDTPR LCDDTPR 7 0 LCDDATA LCDDATA 7 0 TYPE LCDCON0 6 LCDEN LCDCON 7 PWR_SAVE 1 0 LCDPWR 1 0 R_MODE LCDMODE 7 V...

Страница 612: ...or 8 COM pins are used and the SEG pins will be used according to the definition of multiple function pin setting When those SEG pins were used as COM pins these SEG bits are unavailable Each COM pin...

Страница 613: ...be energized Therefore DC voltage applied to LCD electrodes may harm and destroy the LCD The LCD driver waveforms are designed to create 0 Vdd potential across all LCD segments ML51 ML54 ML56 Series...

Страница 614: ...2 3VLCD 1 3VLCD 0 VLCD 2 3VLCD 1 3VLCD 0 VLCD 2 3VLCD 1 3VLCD 0 COM0 COM1 COM2 COM7 SEG0 SEG1 VLCD 2 3VLCD 1 3VLCD 0 VLCD 2 3VLCD 1 3VLCD 0 VLCD 2 3VLCD 1 3VLCD 0 VLCD 2 3VLCD 1 3VLCD 0 VLCD 2 3VLCD...

Страница 615: ...LCD 3 4VLCD 2 4VLCD 1 4VLCD 0 COM7 VLCD 3 4VLCD 2 4VLCD 1 4VLCD 0 VLCD 3 4VLCD 2 4VLCD 1 4VLCD 0 VLCD 3 4VLCD 2 4VLCD 1 4VLCD 0 VLCD 3 4VLCD 2 4VLCD 1 4VLCD 0 VLCD 3 4VLCD 2 4VLCD 1 4VLCD 0 SEG0 VLCD...

Страница 616: ...pump up voltage with limitation VLCD max 1 8 VDD LCD pump down voltage without this limitation Disable 11 Table 6 17 1 VLCD Source Selection Table LCD Driving Current Mode Select And Power Consumption...

Страница 617: ...2 C flags are cleared by software Following table shows the interrupt event condition Control Register Interrupt FLAG Interrupt Condition LCDIE LCDCON0 5 LCDIS LCDCON0 6 LCD Charge Pump Alarm Couter R...

Страница 618: ...ML51 ML54 ML56 Sep 01 2020 Page 618 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL 6 17 5 Register Description...

Страница 619: ...ctions other than LCD 1 LCD circuit ON COM and enabled SEG pins generate the LCD driving waveform 6 TYPE Display Type 0 Type A 1 Type B Power saving mode 5 4 BIAS 1 0 LCD Bias 00 Reserved 01 1 2 bias...

Страница 620: ...S DISP LCDDIV 2 0 R W R W R W Bit Name Description 7 5 Reserved 4 LCDCKS LCD Clock Source Select 0 LIRC 24 1 LXT 24 3 DISP DISP The LCD display keeps display on or display off during chip power down m...

Страница 621: ...3 0000_0000 b 7 6 5 4 3 2 1 0 LCDPTR 4 0 R W Bit Name Description 7 5 Reserved 4 0 LCDPTR 4 0 LCD Data Pointer This field determines which LCD display data register is accessed by LCDDAT It s also me...

Страница 622: ...00_0000 b 7 6 5 4 3 2 1 0 LCDDAT 7 0 R W Bit Name Description 7 0 LCDDAT 7 0 LCD Data This byte is defined which COM pin should be enabled Bit 0 means COM 0 and bit 7 means COM 7 When value 1 written...

Страница 623: ...egister SFR Address Reset Value LCDPWR FDH Page 3 0000_0000 b 7 6 5 4 3 2 1 0 PWR_SAVE 1 0 R W Bit Name Description 7 2 Reserved 1 0 PWR_SAVE 1 0 LCD Power Save Mode Select LCD driving cycle select tu...

Страница 624: ...00 b 7 6 5 4 3 2 1 0 BLINK BLF 2 0 R W R W Address FEH Page 3 Reset value 0000 0000b Bit Name Description 7 4 Reserved 3 BLINK LCD BLINK 0 LCD always on 1 LCD blinking The blinking frequency is based...

Страница 625: ...ODE define and the LCD driving current please reference Table 6 17 2 LCD Driving Mode 0 Disable 1 Enable Note When R_MODE is enabled BUF_MODE should be disabled 6 BUF_MODE Buffer Mode Enable This bit...

Страница 626: ...3 2 1 0 VCP_SEL 5 0 R W Address F1H Page 3 Reset value 0000 0000b Bit Name Description 7 6 Reserved 5 0 VCP_SEL 5 0 Charge Pump Voltage Set Value 000000 5 4V 000101 5 2V 001010 5 0V 001110 4 8V 010011...

Страница 627: ...rupt The LCDCPALIF LCDIF 0 will be set to 1 1 LCD charge pump active counter read interrupt When bit set as 1 If LCDCPIF 1 means LCD module successful to drivring LCD pixel The charge pump value will...

Страница 628: ...mp Alarm Counter Value Low Byte TA Protected Register SFR Address Reset Value LCDCPALCT0 F5H Page 3 TA protected 0000_0000 b 7 6 5 4 3 2 1 0 LCDCPOVCT 7 0 R W Bit Name Description 7 0 LCDCPOVCT 7 0 LC...

Страница 629: ...PALCT1 LCD Charge Pump Alarm Counter Value High Byte TA Protected Register SFR Address Reset Value LCDCPALCT1 E9H Page 3 TA protected 0000_0000 b 7 6 5 4 3 2 1 0 LCDCPOVCT 9 8 R W Bit Name Description...

Страница 630: ...Pump Counter Value Low Byte Register SFR Address Reset Value LCDCPCT0 F6H page3 0000_0000 b 7 6 5 4 3 2 1 0 LCDCPCT 7 0 R Bit Name Description 7 0 LCDCPCT 7 0 LCD Current Frame Chage Pump Counter Valu...

Страница 631: ...PCT1 LCD Charge Pump Counter Value High Byte Register SFR Address Reset Value LCDCPCT1 EAH page3 0000_0000 b 7 6 5 4 3 2 1 0 LCDCPCT 9 8 R W Bit Name Description 7 2 Reserved 1 0 LCDCPCT 9 8 LCD Curre...

Страница 632: ...amage may cause thie result Since as normal the charge pump counter value shoud not reach 0x3FF 1 LCDCPIF LCD Charge Pump Interrupt Flag This Flag check LCDCPCT0 and LCDCPCT1 counter value if LCDIS LC...

Страница 633: ...ly 30 Hz to 100 Hz is also important and needs to carefully give the LCDCLK register a proper value If LXT is used as the LCD clock source user should turn on LXT first by software Otherwise user shou...

Страница 634: ...es Supports real time counter and calendar counter for RTC time and calendar check Supports alarm time and calendar settings Supports alarm time and calendar mask enable settings Selectable 12 hour or...

Страница 635: ...MYEAR RTCCALMMON RTCCALMDAY 1 128 change 1 64 change 1 32 change 1 16 change 1 8 change 1 4 change 1 2 change 1 change sec 111 110 101 100 011 010 001 000 TICK RTCTICK 2 0 TICKIF RTCINTSTS 1 TICKIEN R...

Страница 636: ...ans the RTC registers are read write accessible When executing write RTC register command RWENF RTCRWEN 0 will be clear to 0 The RTC Register Description access attribute when RWENF is 1 and 0 are sho...

Страница 637: ...be 0x00 while the compensation is not executed User can utilize a frequency counter to measure RTC clock source via clock output function in manufacturing In the meanwhile user can use clock output f...

Страница 638: ...EHR RTCCALDAY RTCCALMON and RTCCALYEAR registers are equal to alarm time and calendar values in RTCTALMSEC RTCTALMMIN RTCTALMHR RTCCALMDAY RTCCALMMON and RTCCALMYEAR registers the RTC alarm interrupt...

Страница 639: ...MESEC 3 0 is 0x0 5 The below table shows registers value after both core power and battery power are first powered on Register Reset State RTCINIT 0 RTCRWEN 0x01 RTCCALYEAR 15 year RTCCALMON 8 month R...

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Страница 641: ...ite Only When RTC block is powered on RTC is at reset state User has to write a number 0x 57 to INIT to make RTC leave reset state Once the INIT 7 0 is written as 0x57 the RTC will be in un reset stat...

Страница 642: ...1 0 FADJTG RWENF R W R Bit Name Description 7 2 Reserved 1 FADJTG RTC Counter Update Read and Write Set this bit 1 by software It will update to RTC counter from RTCFREQADJ1 0 After RTC counter update...

Страница 643: ...ries Technical Reference Manual RTCCLKSEL RTC Clock Select Register Register SFR Address Reset Value RTCCLKSEL A3H Page 3 0000_0000 b 7 6 5 4 3 2 1 0 C32KS R W Bit Name Description 7 1 Reserved 0 C32K...

Страница 644: ...e RTCFREQADJ0 A4H Page 3 0000_0000 b 7 6 5 4 3 2 1 0 FRACTION R W Bit Name Description 7 6 Reserved 5 0 FRACTION Fraction Part Formula FRACTION fraction part of detected value X 64 Note Digit in FCR m...

Страница 645: ...1 01010 Integer part of detected value is 32762 01011 Integer part of detected value is 32763 01100 Integer part of detected value is 32764 01101 Integer part of detected value is 32765 01110 Integer...

Страница 646: ...46 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL Bit Name Description Note FREQADJ s counter will be reset for start to Compensatie when write RTCFREQADJ0 1 RTCTIME RTCCAL RTCWEEKDA...

Страница 647: ...1 0 TICKIEN ALMIEN R W R W Bit Name Description 7 2 Reserved 1 TICKIEN Time Tick Interrupt Enable Bit Set TICKIEN to 1 can also enable chip wake up function when RTC tick interrupt event is generated...

Страница 648: ...egister Register SFR Address Reset Value RTCINTSTS A7H Page 3 0000_0000 b 7 6 5 4 3 2 1 0 TICKIF ALMIF R W R W Bit Name Description 7 2 Reserved 1 TICKIF RTC Time Tick Interrupt Flag 0 Tick condition...

Страница 649: ...second Loading Register Register SFR Address Reset Value RTCTIMESEC A9H Page 3 0000_0000 b 7 6 5 4 3 2 1 0 TENSEC 2 0 SEC 3 0 R W R W Bit Name Description 7 Reserved 6 4 TENSEC 2 0 10 Sec Time Digit 0...

Страница 650: ...Register SFR Address Reset Value RTCTIMEMIN AAH Page 3 0000_0000 b 7 6 5 4 3 2 1 0 TENMIN 2 0 MIN 3 0 R W R W Bit Name Description 7 Reserved 6 4 TENMIN 2 0 10 Min Time Digit 0 5 3 0 MIN 3 0 1 Min Tim...

Страница 651: ...3 0000_0000 b 7 6 5 4 3 2 1 0 TENHR 1 0 HR 3 0 R W R W Bit Name Description 7 6 Reserved 5 4 TENHR 1 0 10 Hour Time Digit 0 2 When RTC runs as 12 hour time scale mode RTCTIMEHR 5 the high bit of TENHR...

Страница 652: ...ter Register SFR Address Reset Value RTCCALDAY ADH Page 3 0000_1000 b 7 6 5 4 3 2 1 0 TENDAY DAY R W R W Bit Name Description 7 6 Reserved 5 4 TENDAY 10 Day Calendar Digit 0 3 3 0 DAY 1 Day Calendar D...

Страница 653: ...month Loading Register Register SFR Address Reset Value RTCCALMON AEH Page 3 0000_1000 b 7 6 5 4 3 2 1 0 TENMON MON 3 0 R W R W Bit Name Description 7 5 Reserved 4 TENMON 10 Month Calendar Digit 0 1...

Страница 654: ...gister Register SFR Address Reset Value RTCCALYEAR AFH Page 3 0001_0101 b 7 6 5 4 3 2 1 0 TENYEAR YEAR R W R W Bit Name Description 7 4 TENYEAR 10 Year Calendar Digit 0 9 3 0 YEAR 1 Year Calendar Digi...

Страница 655: ...Value RTCTALMSEC B1H Page 3 0000_0000 b 7 6 5 4 3 2 1 0 TENSEC 2 0 SEC 3 0 R W R W Bit Name Description 7 Reserved 6 4 TENSEC 2 0 10 Sec Time Digit of Alarm Setting 0 5 3 0 SEC 3 0 1 Sec Time Digit o...

Страница 656: ...e 3 0000_0000 b 7 6 5 4 3 2 1 0 TENMIN 2 0 MIN 3 0 R W R W Bit Name Description 7 Reserved 6 4 TENMIN 2 0 10 Min Time Digit of Alarm Setting 0 5 3 0 MIN 3 0 1 Min Time Digit of Alarm Setting 0 9 Note...

Страница 657: ...R W Bit Name Description 7 6 Reserved 5 4 TENHR 1 0 10 Hour Time Digit of Alarm Setting 0 2 When RTC runs as 12 hour time scale mode RTCTIMEHR 5 the high bit of TENHR 1 0 means AM PM indication If RT...

Страница 658: ...0000_0000 b 7 6 5 4 3 2 1 0 TENDAY 1 0 DAY 3 0 R W R W Bit Name Description 7 6 Reserved 5 4 TENDAY 1 0 10 Day Calendar Digit of Alarm Setting 0 3 3 0 DAY 3 0 1 Day Calendar Digit of Alarm Setting 0 9...

Страница 659: ...Value RTCCALMMON B6H Page 3 0000_0000 b 7 6 5 4 3 2 1 0 TENMON MON 3 0 R W R W Bit Name Description 7 5 Reserved 4 TENMON 10 Month Calendar Digit of Alarm Setting 0 1 3 0 MON 3 0 1 Month Calendar Digi...

Страница 660: ...e 3 0000_0000 b 7 6 5 4 3 2 1 0 TENYEAR 3 0 YEAR 3 0 R W R W Bit Name Description 7 4 TENYEAR 3 0 10 Year Calendar Digit of Alarm Setting 0 9 3 0 YEAR 3 0 1 Year Calendar Digit of Alarm Setting 0 9 No...

Страница 661: ...Scale Selection Register Register SFR Address Reset Value RTCCLKFMT B9H Page 3 0000_0001 b 7 6 5 4 3 2 1 0 24HEN R W Bit Name Description 7 1 Reserved 0 24HEN 24 Hour 12 Hour Time Scale Selection Indi...

Страница 662: ...TCWEEKDAY RTC Day of the Week Register Register SFR Address Reset Value RTCWEEKDAY BBH Page 3 0000_0110 b 7 6 5 4 3 2 1 0 WEEKDAY R W Bit Name Description 7 3 Reserved 2 0 WEEKDAY Day of the Week Regi...

Страница 663: ...Series Technical Reference Manual RTCLEAPYEAR RTC Leap Year Indication Register Register SFR Address Reset Value RTCLEAPYEAR BCH Page 3 0000_0000 b 7 6 5 4 3 2 1 0 LEAPYEAR R Bit Name Description 7 1...

Страница 664: ...ed 2 0 TICK 2 0 Time Tick Register These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request 000 Time tick is 1 second 001 Time tick is 1 2 second 010 Time tick is 1...

Страница 665: ...W R W Bit Name Description 7 6 Reserved 5 MTENHR Mask 10 Hour Time Digit of Alarm Setting 0 2 4 MHR Mask 1 Hour Time Digit of Alarm Setting 0 9 3 MTENMIN Mask 10 Min Time Digit of Alarm Setting 0 5 2...

Страница 666: ...escription 7 6 Reserved 5 MTENYEAR Mask 10 Year Calendar Digit of Alarm Setting 0 9 4 MYEAR Mask 1 Year Calendar Digit of Alarm Setting 0 9 3 MTENMON Mask 10 Month Calendar Digit of Alarm Setting 0 1...

Страница 667: ...2 Features Supports up to 14 touch keys reference pad shielding electrode Supports any TK pin as reference pad and any one of CLKO pin as shielding electrode Programmable sensitivity levels for each c...

Страница 668: ...face RTC Tick Reference Reference Touch Key 1 Touch Key 1 Shielding Shielding Touch Key 2 Touch Key 2 Touch Key n Touch Key n Capacitor Bank Polarity Select Capacitor Bank Polarity Select TKx Polarity...

Страница 669: ...Fundamentals The capacitance of the touch key without a finger touch is called as parasitic capacitance CP Parasitic capacitance results from the electric field between the touch key including the sen...

Страница 670: ...CR Capacitor Bank Polarity AV SS Time Voltag e Complement Capacitor Bank for Touch Key Capacitor Bank for Reference counter Touch Key Scan Enabled Cycle CMPX_IN CMPX_IP Figure 6 19 2 Touch Key Sensing...

Страница 671: ...Touch Key Capacitor Bank for Reference CR Reference Pad Reference Pad Touch Key Touch Key CMP Capacitor Bank Polarity Select counter CT CP CMPX_IN CT CMPX_IP CR Touch Key Scan Enabled Cycle Capacitor...

Страница 672: ...assigned as default reference channel automatically if there is no reference channel internl source assigned by user Touch Key controller malfunctions without assigning physical reference channel s to...

Страница 673: ...e RTC to wake up Touch Key controller for key scanning periodically Touch Key controller requests HIRC for key scanning only when waked up and keeps CPU in power down state Interrupts generated when a...

Страница 674: ...ML51 ML54 ML56 Sep 01 2020 Page 674 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL 6 19 6 Register Description...

Страница 675: ...DD 1010 3 32 VDD 1011 4 32 VDD 1100 5 32 VDD 1101 6 32 VDD 1110 7 32 VDD 1111 8 32 VDD 3 SCAN_ALL All Keys Scan Enable This function is used for low power key scanning operation TKDATALL is the only o...

Страница 676: ...00_0000 b 7 6 5 4 3 2 1 0 PULSET SENSET R W R W Bit Name Description 7 Reserved 6 4 PULSET Touch Key Sensing Pulse Width Time Control 000 500ns 001 1us 010 2us 011 4us 100 8us 101 8us 110 8us 111 8us...

Страница 677: ...l 2 Register Register Memory Address Reset Value TKCON2 8002H 0000_0001 b 7 6 5 4 3 2 1 0 POL_INIT POL_CAP R W R W Bit Name Description 7 3 Reserved 2 POL_INIT Touch Key Sensing Initial Potential Cont...

Страница 678: ...bit is ignored if TK5REN TKREN0 5 is 1 0 TKDAT5 is invalid 1 TK5 is always enable for Touch Key scan TKDAT5 is valid 4 TK4SEN TK4 Scan Enable This bit is ignored if TK4REN TKREN0 4 is 1 0 TKDAT4 is in...

Страница 679: ...nvalid 1 TK13 is always enable for key scan TKDAT13 is valid 4 TK12SEN TK12 Scan Enable This bit is ignored if TK12REN TKREN 4 is 1 0 TKDAT12 is invalid 1 TK12 is always enable for Touch Key scan TKDA...

Страница 680: ...s not reference 1 TK6 is set as reference and TKDAT6 is invalid 5 TK5REN TK5 Reference Enable 0 TK5 is not reference 1 TK5 is set as reference and TKDAT5 is invalid 4 TK4REN TK4 Reference Enable 0 TK4...

Страница 681: ...reference and TKDAT14 is invalid 5 TK13REN TK13 Reference Enable 0 TK13 is not reference 1 TK13 is set as reference and TKDAT13 is invalid 4 TK12REN TK12 Reference Enable 0 TK12 is not reference 1 TK1...

Страница 682: ...E R W R W Bit Name Description 7 2 Reserved 1 TKSCIE Touch Key Scan Complete Interrupt Enable 0 Key scan complete without threshold control interrupt is disable 1 Key scan complete without threshold c...

Страница 683: ...TK interrupt if TKSCTHIE TKINTEN 0 bit is enabled 2 TKIF Key Scan Interrupt Flag Read Only 0 No threshold control event with each Key Scan 1 Threshold control event occurs with each Keys Scan This bi...

Страница 684: ...1 Threshold control event occurs with TK6 5 TKIF5 TK5 Interrupt Flag 0 No threshold control event with TK5 1 Threshold control event occurs with TK5 4 TKIF4 TK4 Interrupt Flag 0 No threshold control...

Страница 685: ...with TK14 5 TKIF13 TK13 Interrupt Flag 0 No threshold control event with TK13 1 Threshold control event occurs with TK13 4 TKIF12 TK12 Interrupt Flag 0 No threshold control event with TK12 1 Threshol...

Страница 686: ...00 b TKCCBD3 8013H 0000_0000 b TKCCBD4 8014H 0000_0000 b TKCCBD5 8015H 0000_0000 b TKCCBD6 8016H 0000_0000 b TKCCBD7 8017H 0000_0000 b TKCCBD8 8018H 0000_0000 b TKCCBD9 8019H 0000_0000 b TKCCBD10 801A...

Страница 687: ...Series Technical Reference Manual TKCCBDALL Touch Key Complement Capacitor Bank Data Register Register Memory Address Reset Value TKCCBDALL 801FH 0000_0000 b 7 6 5 4 3 2 1 0 CCBDALL R W Bit Name Descr...

Страница 688: ...000_0000 b REFCBD4 8024H 0000_0000 b REFCBD5 8025H 0000_0000 b REFCBD6 8026H 0000_0000 b REFCBD7 8027H 0000_0000 b REFCBD8 8028H 0000_0000 b REFCBD9 8029H 0000_0000 b REFCBD10 802AH 0000_0000 b REFCBD...

Страница 689: ...echnical Reference Manual REFCBDALL Reference Capacitor Bank Data Register Register Memory Address Reset Value REFCBDALL 802FH 0000_0000 b 7 6 5 4 3 2 1 0 REFCBDALL R W Bit Name Description 7 0 REFCBD...

Страница 690: ...6H 1100_0000 b TKIDLPOL7 8037H 1100_0000 b TKIDLPOL8 8038H 1100_0000 b TKIDLPOL9 8039H 1100_0000 b TKIDLPOL10 803AH 1100_0000 b TKIDLPOL11 803BH 1100_0000 b TKIDLPOL12 803CH 1100_0000 b TKIDLPOL13 803...

Страница 691: ...ERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual Bit Name Description 1 0 IDLSx TKx Idle State Control This register is ignored if both TKxSEN and POLENx are 0 or TKxREN is 1 00 TKx conn...

Страница 692: ...b TKDAT4 8044H 0000_0000 b TKDAT5 8045H 0000_0000 b TKDAT6 8046H 0000_0000 b TKDAT7 8047H 0000_0000 b TKDAT8 8048H 0000_0000 b TKDAT9 8049H 0000_0000 b TKDAT10 804AH 0000_0000 b TKDAT11 804BH 0000_00...

Страница 693: ...ML51 ML54 ML56 Series Technical Reference Manual TKDATALL Touch Key x Data Register Register Memory Address Reset Value TKDATALL 804FH 0000_0000 b 7 6 5 4 3 2 1 0 TKDATALL R Bit Name Description 7 0...

Страница 694: ...1111_1111 b TKHTH3 8053H 1111_1111 b TKHTH4 8054H 1111_1111 b TKHTH5 8055H 1111_1111 b TKHTH6 8056H 1111_1111 b TKHTH7 8057H 1111_1111 b TKHTH8 8058H 1111_1111 b TKHTH9 8059H 1111_1111 b TKHTH10 805AH...

Страница 695: ...L ML51 ML54 ML56 Series Technical Reference Manual TKHTHALL Touch Key x High Threshold Register Register Memory Address Reset Value TKHTHALL 805FH 1111_1111 b 7 6 5 4 3 2 1 0 HTH_ALL R W Bit Name Desc...

Страница 696: ...o other data is needed then only one byte was required Thus the instruction is called a one byte instruction In some cases more data is needed which is two or three byte instructions Following lists a...

Страница 697: ...nce Manual Instruction CY OV AC Instruction CY OV AC ADD X 1 X X CLR C 0 ADDC X X X CPL C X SUBB X X X ANL C bit X MUL 0 X ANL C bit X DIV 0 X ORL C bit X DA A X ORL C bit X RRC A X MOV C bit X RLC A...

Страница 698: ...ve OR XRL direct A and XRL direct data JBC Jump if bit 1 and clear it JBC bit rel CPL Complement bit CPL bit INC Increment INC direct DEC Decrement DEC direct DJNZ Decrement and jump if not zero DJNZ...

Страница 699: ...12 DIVAB 84 1 4 12 DA A D4 1 1 12 ANL A Rn 58 5F 1 2 6 ANL A direct 55 2 3 4 ANL A Ri 56 57 1 4 3 ANL A data 54 2 2 6 ANL direct A 52 2 4 3 ANL direct data 53 3 4 6 ORL A Rn 48 4F 1 2 6 ORL A direct 4...

Страница 700: ...6 MOV Ri data 76 77 2 3 6 MOV DPTR data16 90 3 3 8 MOVC A A DPTR 93 1 4 6 MOVC A A PC 83 1 4 6 MOVX A Ri 1 E2 E3 1 5 4 8 MOVX A DPTR 1 E0 1 4 6 MOVX Ri A 1 F2 F3 1 6 4 MOVX DPTR A 1 F0 1 5 4 8 PUSH d...

Страница 701: ...l 20 3 5 4 8 JNB bit rel 30 3 5 4 8 JBC bit rel 10 3 5 4 8 CJNE A direct rel B5 3 5 4 8 CJNE A data rel B4 3 4 6 CJNE Rn data rel B8 BF 3 4 6 CJNE Ri data rel B6 B7 3 6 4 DJNZ Rn rel D8 DF 2 4 6 DJNZ...

Страница 702: ...PLICATION CIRCUIT 7 1 Power Supply Scheme VDD VSS 0 1uF N 10uF 0 1uF EXT_PWR EXT_VSS as close to VDD as possible as close to the EXT_PWR as possible VREF as close to VREF as possible 1uF L 30S ML51 Se...

Страница 703: ...CS CLK MISO SPI_SS MOSI SPI_CLK SPI_MISO SPI_MOSI DVCC 20pF 20pF 20pF 20pF 10K 32 768 kHz crystal 4 7K 4 7K Crystal Reset Circuit VDD VSS ICE_CLK ICE ICP Interface DVCC 100K 100K 100 100 DH1 DH2 VLCD...

Страница 704: ...Page 704 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL 8 ELECTRICAL CHARACTERISTICS Please refer to the relative Datasheet for detailed information about the ML51 ML54 ML56 Series...

Страница 705: ...020 Page 705 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual 9 PACKAGE DIMENSIONS 9 1 LQFP 64L pin 7 0 x 7 0 x 1 4 mm Figure 9 1 1 LQF...

Страница 706: ...24 0 018 9 10 9 00 8 90 0 358 0 354 0 350 0 50 0 20 0 25 1 45 1 40 0 10 0 15 1 35 0 008 0 010 0 057 0 055 0 026 7 10 7 00 6 90 0 280 0 276 0 272 0 004 0 006 0 053 Symbol Min Nom Max Max Nom Min Dimens...

Страница 707: ...ML56 Sep 01 2020 Page 707 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual 9 3 LQFP 44 pin 10 x 10 x 1 4mm Figure 9 3 1 LFP44 Package...

Страница 708: ...ML51 ML54 ML56 Sep 01 2020 Page 708 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL 9 4 QFN 33 pin 4 0 x 4 0 x 0 8 mm Figure 9 4 1 QFN 33 Package Dimension...

Страница 709: ...56 Sep 01 2020 Page 709 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual 9 5 LQFP 32 pin 7 0 x 7 0 x 1 4 mm Figure 9 5 1 LQFP 32 Packag...

Страница 710: ...ML51 ML54 ML56 Sep 01 2020 Page 710 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL 9 6 TSSOP 28 pin 4 4 x 9 7 x 1 0 mm Figure 9 6 1 TSSOP 28 Package Dimension...

Страница 711: ...e 711 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual 9 7 SOP 28 pin 300mil E 1 28 15 14 Control demensions are in milmeters E Figure...

Страница 712: ...ML51 ML54 ML56 Sep 01 2020 Page 712 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL 9 8 TSSOP 20 pin 4 4 x 6 5 x 0 9 mm Figure 9 8 1 TSSOP 20 Package Dimension...

Страница 713: ...713 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual 9 9 SOP 20 pin 300 mil Figure 9 9 1 SOP 20 Package Dimension E 1 20 11 10 Control...

Страница 714: ...ML51 ML54 ML56 Sep 01 2020 Page 714 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL 9 10 QFN 20 pin 3 0 x 3 0 x 0 8 mm Figure 9 10 1 QFN 20 Package Dimension...

Страница 715: ...Sep 01 2020 Page 715 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL ML51 ML54 ML56 Series Technical Reference Manual 9 11 TSSOP 14 pin 4 4 x 5 0 x 0 9 mm Figure 9 11 1 TSSOP 14 Pack...

Страница 716: ...ML51 ML54 ML56 Sep 01 2020 Page 716 of 719 Rev 2 00 ML51 ML54 ML56 SERIES TECHNICAL REFERENCE MANUAL 9 12 MSOP 10 pin 3 0 x 3 0 x 0 85 mm Figure 9 12 1 MSOP 10 Package Dimension...

Страница 717: ...ency of system clock HIRC 12 MHz Internal High Speed RC Oscillator IAP In Application Programming ICP In Circuit Programming ISP In System Programming LDO Low Dropout Regulator LIRC 10 kHz internal lo...

Страница 718: ...l release 2019 3 18 1 01 Section 3 1 Added package type table Section 4 2 2 Added Multi function summary table Section 7 2 Added description that all about PWM1 register is only for 64K flash body pro...

Страница 719: ...ure Usage Insecure usage includes but is not limited to equipment for surgical implementation atomic energy control instruments airplane or spaceship instruments the control or operation of dynamic br...

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