CHAPTER 10 SERIAL INTERFACE FUNCTION
218
Figure 10-7. Block Diagram of I
2
C
Internal bus
IIC status register
(IICS0)
IIC control register
(IICC0)
Slave address
register (SVA0)
Noise elimination
circuit
Noise elimination
circuit
Coincidence
signal
IIC shift register
(IIC0)
SO latch
IICE
D Q
SET
CLEAR
CL1,
CL0
SDA
SCL
N-ch open
drain output
Data hold
time correction
circuit
ACK detection
circuit
Wake up control
circuit
ACK detection circuit
Stop condition
detection circuit
Serial clock counter
Interrupt request
signal generator
Serial clock control circuit
Serial clock wait
control circuit
Prescaler
INTIIC0
f
xx
TM2 output
CLD
IIC clock select
register (IICCL0)
Internal bus
LREL
WREL
SPIE
WTIM
ACKE
STT
SPT
MSTS
ALD
EXC
COI
TRC
ACKD
STD
SPD
Start condition
detection circuit
DAD
SMC
DFC
CL1
CL0
Содержание V850/SA1 mPD703015
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