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CHAPTER 10 SERIAL INTERFACE FUNCTION
215
Figure 10-5. Format of Serial Operation Mode Registers 0-2 (CSIM0-CSIM2) (2/2)
SCLn2
SCLn1
SCLn0
Clock Selection
0
0
0
External clock input (SCKn)
0
0
1
when n = 0 : TO2
when n = 1, 2 : TO3
0
1
0
fxx/8 (2.125 MHz)
0
1
1
fxx/16 (1.0626 MHz)
1
1
0
fxx/32 (531.3 kHz)
1
1
1
fxx/64 (265.6 kHz)
Others
Setting prohibited
Remarks 1.
Parenthesized values apply when fxx = 17 MHz.
2.
Refer to Figure 10-3 for the SCLn2 bit.
(ii) Communication Operations
In 3-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is sent or received
in synchronized with the serial clock.
The serial I/O shift register n (SIOn) is shifted in synchronized with the falling edge of the serial clock.
Transmission data is held in the SOn latch and is output from the SOn pin. Data that is received via the SIn
pin in synchronized with the rising edge of the serial clock is latched to SIOn.
Completion of an 8-bit transfer automatically stops operation of SIOn and sets the interrupt request flag
(INTCSIn).
Figure 10-6. Timing of 3-wire Serial I/O Mode
SI0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
INTCSIn
Serial clock
1
SO0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
2
3
4
5
6
7
8
Transfer completion
Transfer starts in synchronized with the serial clock’s falling edge
Содержание V850/SA1 mPD703015
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