NEC uPD72257, Предварительное руководство пользователя

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Table 6-4 RGB(565) data arrangement
FIFO entry bit 31 to 16 bit 15 to 0
0 pixel 1 pixel 0
1 pixel 3 pixel 2
... ... ...
31 pixel 63 pixel 62
Above table reflects also the ordering of the captured Video Input data in the
framebuffer.
Caution
Because the FIFO is reset at the beginning of each new scanline, any data left in
the FIFO, that has not been transferred to the framebuffer, gets lost at that point
in time.
Note that no FIFO overflow interrupt VInFFOINT is generated in that situation.
FIFO status The fill status of the FIFO can be monitor. It is reflected in
VInSTATUS.FFUSEDW[5:0], that shows the current number of 32-bit words,
stored in the FIFO.
FIFO overflow If the FIFO is filled with data, waiting for beeing transferred to the framebuffer,
while new data is handed over from the dithering unit to be stored in the FIFO, a
FIFO overflow error occurs, indicated by the interrupt VInFFOINT.
This situation reveals a lack of AHB bus bandwidth and may require to reduce the
AHB bus bandwidth demand of other modules.
6.8.2 Framebuffer addressing
Depending on the capture mode the video data is stored to either one or two
framebuffers in the memory.
The framebuffer address, the FIFO content is written to, is defined by registers:
• VInSTARTADDR1: base address of first field framebuffer
denotes the address of the first pixel of the first field
• VInSTARTADDR2: base address of second field framebuffer
denotes the address of the first pixel of the secondfield
The framebuffer base address must be aligned to 8 pixels, i.e. 16 byte in the
memory, thus the lower 4 bit of each address is fixed to 0000
B
.
In interlaced capture mode the data of each field is stored in separate
framebuffers, addressed by VInSTARTADDR1 and VInSTARTADDR2.
In progressive capture mode only VInSTARTADDR2 determines the framebuffer
base address.
At the beginning of each new field the base addresses in VInSTARTADDR1
respectively VInSTARTADDR2 are copied to internal buffer address registers,
which are incremented during the video data transfer from the FIFO to the
framebuffer. The content of the base address registers remain unmodified.
If new framebuffers shall be used to store the video data, VInSTARTADDR1/
VInSTARTADDR2 must be rewritten. Since a new base address becomes
effective always with the start of a new field, it must be ensured, that the previous
Chapter 6 Video Input (Ravin-M only)
168
Preliminary User's Manual S19203EE1V3UM00