NEC uPD72257, Предварительное руководство пользователя

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9.6.2.3 MEMSTMG1R - SDRAM timing register 1
This register defines various timing parameters of the SDRAM initialization phase
after system start-up.
All values are given in system clock periods 1/f
HCLK
.
Access This register can be read/written in 32-bit units.
Address <MemC_Base> + 08
H
Initial Value 0007 0008
H
. This register is initialized by any reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 INITREF[3:0]
R R R R R R R R R R R/W R/W R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TINIT[15:0]
R/W
Writing to the read-only bits is ignored, reading returns undefined values.
Caution
The default value "0" of bits 21 and 20 must not be changed.
Bit Bit name Function
19 to 16 INITREF[3:0]
INITREF[3:0] defines the number of auto-refreshes during initialization of the SDRAM.
0
H
1 refresh
1
H
2 refreshes
... ...
7
H
8 refreshes (default)
... ...
F
H
16 refreshes
15 to 0 TINIT[15:0]
TINIT[15:0] defines the time to hold SDRAM inputs stable after power-up, before issuing
any commands.
0000
H
0 clock
0001
H
1 clocks
... ...
0008
H
8 clocks (default)
... ...
FFFF
H
65535 clocks
External Memory Interface Controller Chapter 9
Preliminary User's Manual S19203EE1V3UM00
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