NAiS FP1, Руководство по оборудованию

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Outline Divides the 32-bit data by the divisor and stores the result in the specified
area and the remainder in special data registers DT9016 and DT9015.
Program example
■
Operands
■
Explanation of example
• Divides the contents of data registers DT201 and DT200 by the contents of data registers DT101 and DT100 when
trigger X0 turns ON. The quotient is stored in data registers DT1 and DT0 and the remainder is stored in special
data registers DT9016 and DT9015.
Bit position
DT101
0 0 0 0 0 0 0 0
11 8
0 0 0 0
1 0 0 1
3 0
Divisor [S2+1, S2]: K589828
15
• •
12
• • • •
7 4
• •
Bit position
DT1
0 0 0 0 0 0 0 0
11 8
0 0 0 0
0 0 0 0
3 0
Quotient [D+1, D]: K28
15
• •
12
• • • •
7 4
• •
Bit position
DT100
0 0 0 0 0 0 0 0
11 8
0 0 0 0
0 1 0 0
3 0 15
• •
12
• • • •
7 4
• •
Bit position
DT0
0 0 0 0 0 0 0 0
11 8
0 0 0 1
1 1 0 0
3 0 15
• •
12
• • • •
7 4
• •
# # # # # # # # # # # # # # # # # # #
higher 16-bit area
# # # # # # # # # # # # # # # # # # #
higher 16-bit area
# # # # # # # # # # # # # # # # # # #
lower 16-bit area
# # # # # # # # # # # # # # # # # # #
lower 16-bit area
Bit position
DT201
0 0 0 0 0 0 0 1
11 8
0 0 0 0
0 0 1 0
3 0
Dividend [S1+1, S1]: K16908416
15 • • 12 • • • • 7 4 • • Bit position
DT200
0 0 0 0 0 0 0 0
11 8
1 0 0 0
0 0 0 0
3 0 15 • • 12 • • • • 7 4 • •
# # # # # # # # # # # # # # # # # # #
higher 16-bit area
# # # # # # # # # # # # # # # # # # #
lower 16-bit area
Bit position
DT9016 0 0 0 0 0 0 0 0
11 8
0 0 0 0 0 1 1 0
3 0
Remainder: K393232
15
• •
12
• • • •
7 4
• •
Bit position
DT9015 0 0 0 0 0 0 0 0
11 8
0 0 0 1 0 0 0 0
3 0 15
• •
12
• • • •
7 4
• •
# # # # # # # # # # # # # # # # # # #
higher 16-bit area
# # # # # # # # # # # # # # # # # # #
lower 16-bit area
–
X0: ON
Timer/Counter
EV
Relay
SV WR WY WX
Operand
S1 A A A A
A:
N/A: Not Available
Register
DT
A
IY IX
A N/A
H K
A A
Constant
Index
modifier
A
Index
register
Available
A
S2 A A A A A A N/A A A A A
N/A A A A A A N/A N/A N/A A A D
6-3. Description of High-level Instructions
F33
(D%)
32-bit data [(S1+1, S1)/(S2+1, S2)
→ (D+1, D) ... (DT9016, DT9015)]
32-bit equivalent constant or lower 16-bit area of 32-bit data (for dividend)
32-bit equivalent constant or lower 16-bit area of 32-bit data (for divisor)
Lower 16-bit area of 32-bit data (for quotient)
(remainder is stored in special data registers DT9016 and DT9015)
Ladder Diagram
Boolean Non-ladder
Address Instruction
20
X0
F33 D% , DT 200 , DT 100 , DT 0
D
Trigger
S2 S1
20
21
ST X 0
F 33 (D% )
DT 200
DT 100
DT 0
S1
S2
D
Availability Step
11
C24, C40, C56,
and C72 series
179