LeCroy Waverunner2 LT262 Series, Руководство по обслуживанию

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SDRAM
The SDRAM circuit consists of one DIMM module, from 64MB to a maximum of
512MB. The DIMM module type is 168pin SDRAM, 3.3V unbuffered CL=2. The
SDRAM control circuit is built with one CPLD, and several gate ICs.
The SDM (IC87) located on the main control circuit generates all types of bus cycle
timing (normal R/W, 2-beat/8-beat bursts of R/W), refresh cycles. Furthermore, the
SDM has a register for setting the DIMM size, in order to adjust the memory
mapping so as not to have gaps in memory mapping according with the memory
capacity. Two multiplexers (IC9 and IC10) switch the address lines of odd and even
addresses to be connected with the address lines of each DIMM.
Normal Access Timing
This is the simplest access possible: the processor puts an address onto the
address bus and reads or writes the required data out of or to the SDRAM which
corresponds with the bus. The bus width is 32bits, or 4bytes wide, and the CPU
performs to read or write operations (of one through four bytes) which are chained in
a bus cycle.
Burst Access Timing
A burst access, on the 603e configured with 32bit device operation, performs either
two or eight successive reads in SDRAM (2-beat or 8-beat burst access). The idea
is to put the beginning of an address onto the address bus and read/write data out of
or to the SDRAM every clock cycle, without incrementing the address required by
the processor (this is to be achieved by the SDRAM's Burst mode). The 8-beat
access is indicated by an active "low" of NTBST signals and a 32bit access signal
(SIZ2..0=011), and the 2-beat access is indicated by an active "high" of NTBST
signals and an access size of 64 bits (SIZ2..0=100).
Refresh Timing
The 32 KHz clock from the RTC chip is used to generate the timing to refresh
SDRAM. Without this clock, the SDRAM would not be refreshed and all the data in it
would be erased. SDM detects the rising edge and the falling edge of this 32KHz
clock. At the each edge, it generates the refresh cycles.
The arbitration logic between other accesses (bus cycle with the processor and DMA
cycle) and refresh cycles reside in the SDM.
Theory of Operation 4-3