Lattice Semiconductor LatticeECP3 Versa, Руководство пользователя

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LatticeECP3 Serial Protocol Board – Revision E
User’s Guide
loop bandwidth, jitter can be cleaned. For the CDC7005, a low loop (sub 10 Hz) bandwidth can be selected easily.
The CDC7005 itself adds a low noise to its outputs. For jitter cleaning operation, the noise performance of VCXO is
critical. So, with a proper loop bandwidth and applicable VCXO, the CDC7005 acts as a jitter cleaner. The evalua-
tion board is equipped with an Epson-Toyocom TCO2111-245.76MHZ VCXO that is packaged in a 13.9x9.8mm
SMT form-factor.
Table 12. CDC7005 Control and Status Signals
CDC7005 Pin Board Feature Description
1 NPD SW5
Push-button that asserts LOW when depressed to power-down
CDC7005.
14 NRESET SW6 Push-button that asserts LOW when depressed to RESET CDC7005.
22 STATUS_VCXO D13 Amber LED - CDC7005 PLL locked when lit.
23 STATUS REF D14 Amber LED - CDC7005 valid clock on REF_IN when lit. > 3.5 MHz.
25 STATUS LOCK D15
Amber LED - CDC7005 valid VCXO clock on VCXO_IN when lit.
> 10 MHz
The serial interface of the CDC7005 is a simple SPI-compatible interface for writing to the registers of the device. It
consists of three control lines: CTRL_CLK, CTRL_DATA, and CTRL_LE. These pins from the CDC7005 are inter-
connected to the FPGA to allow for a controller to be built inside the FPGA.
Table 13. CDC7005 Serial Interconnections
CDC7005 1156 fpBGA Ball Number
CTRL_CLK 35 E23
CTRL_DATA 33 C23
CTRL_LE 36 E22
The TI CDC7005 can also be controlled via an interface to header J47. This header can be used in conjunction
with the TI programming software required for programming the internal control register of the CDC7005. TI. The
software package provides real-time GUI control to the device. The software runs under Windows98, NT, and 2000.
Info can be found at www.ti.com/lit/zip/scac037.
Table 14. External Programming Interface for TI CDC7005 Clock Cleaner (See Appendix A, Figure 27)
J47 Pin DB-25 Parallel Cable Description
1 2 Data
2 3 CLK
3 4 LE
4 18 Enable
5 19 GND
FPGA Test Pins
(see Appendix A, Figure 31)
General Purpose DIP Switch
(see Appendix A, Figure 31, SW14)
General-purpose FPGA pins are available for user applications. FPGA pins are connected to a switch (SW15) that
is a SPST-side actuated DIP switch. The switch is physically located on the secondary side of the board along the
back-panel edge. The switches are connected to logic level 0 when depressed toward the board and a 1 when
away from the board. The designated pins are connected according to the following table.