Lattice Semiconductor LatticeECP3 Versa, Руководство пользователя

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27
LatticeECP3 Serial Protocol Board – Revision E
User’s Guide
Appendix A. Schematic
Figure 20. Cover Page
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ECP3
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11
6
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day
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Ti
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Siz
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Sheet
of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3
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PB Eva
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a
rd
5.
0
Cov
e
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age
C
11
6
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2009
Board Layout
4- Duplex SERDES Channels- Quad PCSB
8- User IO==> LEDS
Config Status LEDs
8- User IO==> SWITCHES
Logic Analyzer Interface to FPGA IO
User GSRn FPGA PROGRAMn
Power Input
User IO Header 16 GPIO
PCIe X4 4-Duplex SERDES Channels
Power
(Sheet 2)
(Sheet 4)
FPGA Power Pins
(Sheet 9, 10, 13)
(Sheet 11,12)
Programming
(Sheet 5)
PCSA
(Sheet 13, 14)
(Sheet 13, 14)
Bank
8
ECP3
(Sheet 13)
Bank 0
Bank 3
FPGA
LEDs Switches GPIO- SMAs
Bank 6
Test Pins Logic Analyzer
Bank 7
Bank 1
Bank 2
SMAs
Power Mgt.
(Sheet 3)
DQ Test Loops
(Sheet 15)
USB RS232
Ethernet PHY
16-Seg TI CDC
(Sheet 8, 13)
DDR2 32-bit
SERDES
PCSB
PCSC
X4 PCIe
SGMII SATA Tgt & Host Test SMA
(Sheet 7)