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LatticeECP3 Serial Protocol Board – Revision E
User’s Guide
Introduction
The LatticeECP3 Serial Protocol Board (referred to in this document as “SPB”) allows designers to investigate and
experiment with the features of the LatticeECP3 high-speed SERDES transceivers. The SPB is available for full
and detailed characterization of the high speed I/O channels and includes interfaces for some of the latest protocol
interconnections.
Important:
This document (including the schematics in the appendix) describes LatticeECP3 Serial Protocol
Boards marked as
Rev E
. This marking can be seen on the silkscreen of the printed circuit board, under the Lattice
Semiconductor logo.
The features of the LatticeECP3 Serial Protocol Board can assist engineers with rapid-prototyping and testing their
specific designs. The board is an enhanced form-factor of the PCI Express add-in card specification. It allows for x4
PCI Express interconnection that is available for demonstration purposes with some non-standard form-factor
issues. The board has several debugging and analyzing features for complete evaluation of the LatticeECP3
device. This guide is intended to be referenced in conjunction with evaluation design tutorials to demonstrate the
LatticeECP3 FPGA.
The evaluation board includes provisioning to connect high-speed SERDES channels via SMA connectors to test
and measurement equipment. The board is manufactured using standard FR4 dielectric and through-hole vias.
The nominal impedance is 50-ohm for single-ended traces and 100-ohm for differential traces.
Figure 1. LatticeECP3 Serial Protocol Board - Revision E
Board Features
• PCI Express x4 edge connector interfaces
– Allow demonstration of PCI Express (x4) interfaces