5
LatticeECP3 Serial Protocol Board – Revision E
User’s Guide
Table 3. Power Supply Test Connections
Test Point Designator
Supply
LP1
2.5V
LP2
1.5V
LP3
3.3V
LP4
1.8V
LP5
1.2V VCCA
LP6
1.2V VCC Core
PCI Express Power Interface
Power can be sourced to the board via the PCB edge fingers (CN1). This interface allows the user to provide power
from a PCI Express host board.
Power Management
The evaluation board includes a Lattice ispPAC
®
-POWR1220AT8 programmable power management IC (U10).
This device controls the power sequence and monitors designated board supplies. The POWER GOOD indication
LEDS are controlled via this device.
The power management device is factory programmed to control the power supplies. A block diagram of the power
management is shown in Figure 3.
Figure 3. Power Management Block Diagram
VCC Core, +1.2v , 10A
3_3V, +3.3V, 2A
3.3VIN, +2.5V, 6A
1_5V, +1.5V, 2A
ispPAC
12V INPUT
PCIe Edge
12V Wall Adapter
12V Input Terminal
MOSFET
1_8V, +1.8V, 2A
1_2VA, +1.2V, 1.5A
2_5V, +2.5V, 1.5A
LDO
LDO
LDO
LDO
POL
POL
LDO
ETH_1_2V, +1.2V, 0.5A
Programming/FPGA Configuration
(see Appendix A, Figure 23)
A programming header is provided on the evaluation board, providing access to the LatticeECP3 JTAG port.
Note: An ispDOWNLOAD™ Cable is included with each ispLEVER
®
-Base or ispLEVER-Advanced design tool
shipment. Cables may also be purchased separately from Lattice.
ispVM Download Interface
J12 is an 10-pin JTAG connector used in conjunction with the ispVM USB download cable to program and control
the device.