22
LatticeECP3 Serial Protocol Board – Revision E
User’s Guide
Table 21. PHY Hardware Configuration Switch Control (see Appendix A, Figure 29)
Switch
Position
88E1111 LED
Output
Bit[2:0]
88E1111 Hardware Register Map
1
VDDO
111
DIP
88E1111 Pin
Bit[2]
Bit[1]
Bit[0]
2
LED_10
110
SW7
CONFIG0
PHYADDR[2] PHYADDR[1]
PHYADDR[0]
3
LED_100
101
SW8
CONFIG1
ENE_PAUSE PHYADDR[4]
PHYADDR[3]
4
LED_1000
100
SW9
CONFIG2
ANEG[3]
ANEG[2]
ANEG[1]
5
LED_DUPLEX
011
SW10
CONFIG3
ANEG[0]
ENA_XC
DIS_125
6
LED_RX
010
SW11
CONFIG4
MODE[2]
MODE[1]
MODE[0]
7
LED_TX
001
SW12
CONFIG5
DIS_FC
DIS_SLEEP
MODE[3]
8
VSS
000
SW13
CONFIG6
SEL_BDT
INT_POL
75/50 Ohm
Note: DIP switches SW[7:13] utilize same position mapping.
Table 22. Board DIP Switch Designations for Marvell Transceiver Configuration Pins
Switch
PHY
Configuration Pin
SW7
CONFIG0
SW8
CONFIG1
SW9
CONFIG2
SW10
CONFIG3
SW11
CONFIG4
SW12
CONFIG5
SW13
CONFIG6
Figure 19. DIP Switch Positions for CONFIG Pins
On
Off
VCC0
1
LED LINK10
2
LED LINK100
3
LED LINK100
4
LED DUPLEX
5
LED RX
6
LED TX
7
VSS
8