23
LatticeECP3 Serial Protocol Board – Revision E
User’s Guide
Table 23. Marvel Transceiver Configuration Defaults
DIP Switch
PHY Config
Pin
Position
ON
Encoded
Output Pin
Encoded
Value
Description
SW7
CONFIG0
7
LED TX
001
PHY ADDR[2:0] = 001
SW8
CONFIG1
4
LED
LINK1000
100
ENABLE PAUSE, PHY ADDR[4:3] = 00
SW9
CONFIG2
1
VCCO
111
Auto Neg., Advertise All, Prefer Slave
SW10
CONFIG3
1
VCCO
111
Enable MDI Crossover, Disable 125 CLK
SW11
CONFIG4
8
VSS
000
1000 Base-X without clock 1000 Base-X Auto Neg. to
copper (GBIC)
SW12
CONFIG5
2
LED
LINK10
110
Disable fiber/copper, Auto-detect, Enable Sleep
SW13
CONFIG6
8
VSS
000
Select MDC/MDIO, INTn Active High, 50-ohm termination
Table 24. FPGA/MAC to 88E1111 PHY Interconnections (see Appendix A, Figure 33)
MAC Netname
88E1111 Pin
1156 fpBGA Ball Number
GTXCLK
E2
A18
TX_CLK
D1
J17/PCLKT0_0
TX_ER
F2
K20
TX_EN
E1
B19
TXD7
J2
A19
TXD6
J1
H19
TXD5
H3
G19
TXD4
H1
F18
TXD3
H2
D18
TXD2
G3
H18
TXD1
G2
J18
TXD0
F1
B18
RX_CLK
C1
E19/PCLKT1_0
RX_ER
D2
L19
RX_DV
B1
C19
RXD7
C5
C20
RXD6
A2
G21
RXD5
A1
G20
RXD4
C4
B20
RXD3
B3
A20
RXD2
C3
K19
RXD1
D3
J19
RXD0
B2
D19
CRS
B5
A17
COL
B6
B17
S_IN+
A3
AP23
S_IN-
A4
AN23
S_CLK+
A5
nc
S_CLK-
A6
nc
S_OUT+
A7
AL23
S_OUT-
A8
AK23