16
LatticeECP3 Serial Protocol Board – Revision E
User’s Guide
DC coupled top-mounted SMA connectors connect to the one quad or four SERDES Tx and Rx channels. These
pins are directly coupled to the designated SMA connector creating a path for both input and output differential
data.
Table 8. SERDES SMA Test Connectors
Connector
SERDES Signal
FPGA Pin
Connector
SERDES Signal
FPGA Pin
J13
PCSB_HDINP0
AL17
J21
PCSB_HDINP2
AL15
J14
PCSB_HDINN0
AK17
J22
PCSB_HDINN2
AK15
J15
PCSB_HDINP1
AL16
J23
PCSB_HDINP3
AL14
J16
PCSB_HDINN1
AK16
J24
PCSB_HDINN3
AK14
J17
PCSB_HDOUTP0
AP17
J25
PCSB_HDOUTP2
AP15
J18
PCSB_HDOUTN0
AN17
J26
PCSB_HDOUTN2
AN15
J19
PCSB_HDOUTP1
AP16
J27
PCSB_HDOUTP3
AP14
J20
PCSB_HDOUTN1
AN16
J28
PCSB_HDOUTN3
AN14
Serial ATA Channels
(see Appendix A, Figure 26)
High-speed connections are included to attach SATA-type cables to SERDES channels for board-to-board or loop-
back purposes. The connectors are configured using the 7-pin SATA specifications.
Figure 18. SATA Connector, Molex Part Number 67800-5050
Table 9. SERDES to SATA Connections
Host
Target
CN1 Pin
SERDES Pin
FPGA Ball #
CN2 Pin
SERDES Pin
FPGA Ball #
1
—
GND
1
—
GND
2
PCSC_HDOUTP1
AP24
2
PCSC_HDINP0
AL25
3
PCSC_HDOUTN1
AN24
3
PCSC_HDINN0
AK25
4
—
GND
4
—
GND
5
PCSC_HDINP1
AL24
5
PCSC_HDOUTP0
AP25
6
PCSC_HDINN1
AK24
6
PCSC_HDOUTN0
AN25
7
—
GND
7
—
GND
SERDES PCI Express Channels
(see Appendix A, Figure 26)
This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edge
fingers (CN3) to fit directly into a PCI Express host receptacle. Power can be supplied directly from the PCI
Express host via the edge-finger connections.