Lattice Semiconductor LatticeECP3 Versa, Руководство пользователя

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LatticeECP3 Serial Protocol Board – Revision E
User’s Guide
Table 10. x4 PCI Express Connections
CML Pin Name FPGA Pin
PCI
Express
PCI Express
Edge Description
PCSA_HDOUTP_3 AP18 PERp0 A16
Integrated end point block transmit pair
PCSA_HDOUTN_3 AN18 PERn0 A17
PCSA_HDINP_3 AL18 PETp0 B14
Integrated end point block receive pair
PCSA_HDINN_3 AK18 PETn0 B15
PCSA_HDOUTP_2 AP19 PERp1 A21
Integrated end point block transmit pair
PCSA_HDOUTN_2 AN19 PERn1 A22
PCSA_HDINP_2 AL19 PETp1 B19
Integrated end point block receive pair
PCSA_HDINN_2 AK19 PETn1 B20
PCSA_HDOUTP_1 AP20 PERp2 A25
Integrated end point block transmit pair
PCSA_HDOUTN_1 AN20 PERn2 A26
PCSA_HDINP_1 AL20 PETp2 B23
Integrated end point block receive pair
PCSA_HDINN_1 AK20 PETn2 B24
PCSA_HDOUTP_0 AP21 PERp3 A29
Integrated End point block transmit pair
PCSA_HDOUTN_0 AN21 PERn3 A30
PCSA_HDINP_0 AL21 PETp3 B27
Integrated End point block receive pair
PCSA_HDINN_0 AK21 PETn3 B28
PCSA_REFCLKP AH19 PCIe_CLKp A13
Integrated End point block differential clock pair
PCSA_REFCLKN AH20 PCIe_CLKn A14
PCIE_PERSETN D23 PERSTN A11 Fundamental PCI Express reset
External SERDES Reference Clock Cleaner
(see Appendix A, Figure 27)
The Texas Instruments CDC7005 is a high-performance, low-phase noise, and low-skew clock synthesizer and jit-
ter cleaner that synchronizes the voltage controlled crystal oscillator (VCXO) frequency to the reference clock. It is
included on the evaluation board to demonstrate the use of an external clock cleaner as a means to reuse the
SERDES recovered clock for retransmitting. The interconnection from the FPGA brings a single-ended LVCMOS
clock from the SERDES to the CDC7005 input. The CDC7005 has an internal prescaler, phase frequency detector,
charge pump, operational amplifier, and a LVPECL clock buffer. Along with an external VCXO and loop filter, the
device completes a phase locked loop (PLL). Through the PLL operation, the VCXO input clock synchronizes with
the reference clock input and ultimately with all clock outputs. All LVPECL clock outputs are completely synchro-
nized in terms of phase and frequency with the reference clock input.
Table 11. Reference Clock Interconnections
CDC7005 Outputs 1156 fpBGA Inputs Notes
Y0/Y0b P46/P47 PCSB_REFCLKP/N AH15/AH16
Stuffing option R126/R127 must be fitted
with 0-ohm resistors for connection to the
FPGA reference clock input.
Y1/Y1b P3/P4 RLM1_GPLLT_INA/B Y28/Y27
Y2/Y2b P7/P8 RUM0_GDLLT_INA/B AJ34/AK34
CDC7005 Input 1156 fpBGA Output
REFIN P37 D22 LVCMOS
The jitter cleaning action depends on the PLL loop bandwidth. Up to the loop bandwidth, all noise (jitter) passes
through and above the loop bandwidth, all signal noise is cleaned. The ideal loop bandwidth is chosen such that
the reference clock source starts exceeding the VCXO noise floor. If the input has lot of jitter, then selecting a low