Lattice Semiconductor LatticeECP3 Versa, Руководство пользователя

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36
LatticeECP3 Serial Protocol Board – Revision E
User’s Guide
Figure 29. PHY Configuration
5 5
4 4
3 3
2 2
1 1
D
D
C
C
B
B
A
A
ETH_ CFG0
ETH_ CFG1
ETH_ CFG3
ETH_ CFG4
ETH_ CFG2
ETH_ CFG6
ETH_ CFG5
E
T
H
_LE
D
_1000
E
T
H
_LE
D
5
ET
H_
L
E
D_
1
0
0
E
T
H
_
L
ED4
ET
H_
L
E
D_
DUPL
EX
ET
H_
L
E
D2
ET
H_
L
E
D_
RX
ET
H_
L
E
D1
ET
H_
L
E
D_
T
X
ET
H_
L
E
D0
E
T
H
_LE
D
_10
E
T
H
_LE
D
3
2_5V
ETH_
CFG
[0
..
6
]
9
E
T
H
_
L
E
D
[0
..5
]
9
Ti
tl
e
Si
z
e
Pr
o
je
c
t
R
e
v
Da
te
:
S
h
e
e
t
of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3
SPB Ev
a
l Bo
a
rd
5.
0
PHY
CONF
IG
URAT
IO
N
B
10
16
Thur
sday,
A
u
gust
13,
2009
Ti
tl
e
Si
z
e
Pr
o
je
c
t
Re
v
Da
te
:
S
h
e
e
t
of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3
SPB Ev
a
l Bo
a
rd
5.
0
PHY
CONF
IG
URAT
IO
N
B
10
16
Thur
sday,
A
u
gust
13,
2009
Ti
tl
e
Si
z
e
Pr
o
je
c
t
Re
v
Da
te
:
S
h
e
e
t
of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3
SPB Ev
a
l Bo
a
rd
5.
0
PHY
CONF
IG
URAT
IO
N
B
10
16
Thur
sday,
A
u
gust
13,
2009
ONLY ONE SWITCH PER DIP PACK CAN BE ACTIVE AT A TIM
E
SW
1
0
TD
A D
IP-
8
SW
1
0
TD
A D
IP-
8
SW
7
TD
A D
IP-
8
SW
7
TD
A D
IP-
8
SW
9
TD
A D
IP-
8
SW
9
TD
A D
IP-
8
SW
1
1
TD
A D
IP-
8
SW
1
1
TD
A D
IP-
8
SW
8
TD
A D
IP-
8
SW
8
TD
A D
IP-
8
SW
1
3
TD
A D
IP-
8
SW
1
3
TD
A D
IP-
8
SW
1
2
TD
A D
IP-
8
SW
1
2
TD
A D
IP-
8