Kontron CP6500-V, Руководство пользователя

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CP6500-V Introduction
ID 28945, Rev. 01 © 2005 Kontron Modular Computers GmbH Page 1 - 11
P R E L I M I N A R Y
2894
5.01.UG.VC.050304/09095
1
1.6 Technical Specification
Table 1-2: CP6500-V Main Specifications
CP6500-V SPECIFICATIONS
P
rocessor and Memory
CPU
The CP6500-V supports the following microprocessors:
•
Intel Celeron with 256 kB L2 cache
•
400 MHz version with 100 MHz PSB in 479 µFCBGA
•
1.0 GHz version with 133 MHz PSB in 479 µFCBGA
Memory Main Memory:
•
Up to 512 MB SDRAM memory without ECC via one 144-pin SODIMM
socket running at 100 MHz
Cache structure:
•
32 kB L1 on-die full speed processor cache
•
16 kB for instruction cache
•
16 kB for write-back data cache
•
Up to 256 kB L2 on-die full speed processor cache
FLASH Memory:
•
8 Mbit Firmware Hub (FWH) for BIOS
Memory Extension:
•
CompactFlash socket type II (true IDE mode with DMA capability)
Serial EEPROM:
•
24LC64 (8 kB) for storing CMOS data when operating without battery
Chi
ps
ets
Intel 815-B0 GMCH 815-B0 Graphics Memory Controller Hub (GMCH)
•
Support for a single Celeron microprocessor
•
64-bit AGTL-based System Bus interface at 100 MHz for 400 MHz pro-
cessor and 133 MHz for 1GHz processor
•
64-bit System Memory interface with support for SDRAM memory at
100 MHz
•
Integrated 2D and 3D Graphics Engines
•
Integrated H/W Motion Compensation Engine
•
Integrated 230 MHz DAC
Intel ICH4 Chipset Intel ICH4 I/O Controller Hub
•
PCI Rev. 2.2 compliant with support for 32-bit/33 MHz PCI operations
•
Power management logic support
•
Enhanced DMA controller, interrupt controller, and timer functions
•
Integrated IDE controller Ultra ATA/100/33
•
USB 2.0 host interface with up to four USB ports available on the
CP6500-V
•
System Management Bus (SMBus) compatible with most I²C™ devices
•
Low Pin Count (LPC) interface
•
Firmware Hub (FWH) interface support