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JN-DS-JN5142 1v0
© NXP Laboratories UK 2012
where the hardware controls the value of the generated RTS (negated if the receive FIFO fill level is greater than a
programmable threshold of 8, 11, 13 or 15 bytes), and only transmits data when the incoming CTS is asserted.
Software can read characters, one byte at a time, from the Receive FIFO and can also write to the Transmit FIFO,
one byte at a time. The Transmit and Receive FIFOs can be cleared and reset independently of each other. The
status of the transmitter can be checked to see if it is empty, and if there is a character being transmitted. The status
of the receiver can also be checked, indicating if conditions such as parity error, framing error or break indication
have occurred. It also shows if an overrun error occurred (receive buffer full and another character arrives) and if
there is data held in the receive FIFO.
The UART is accessed, depending upon the configuration, on DIO4 to DIO7 or DIO12 to DIO15. This is enabled
under software control. The following table details which DIO are used for the UART depending upon the
configuration.
Signal
DIO Assignment
Standard pins
Alternative pins
CTS0
26
36
RTS0
27
37
TXD0
28
38
RXD0
29
40
Table 6: UART IO
If CTS and RTS are not required on the device‟s external pins, then they may be disabled, this allows the DIOx
function to be used for other purposes.
Note: With the automatic flow control threshold set to 15, the hardware flow control within the UART block negates
RTS when the receive FIFO is about to become full. In some instances it has been observed that remote devices that
are transmitting data do not respond quickly enough to the de-asserted CTS and continue to transmit data. In these
instances the data will be lost in a receive FIFO overflow.
13.1 Interrupts
Interrupt generation can be controlled for the UART block, and is divided into four categories:
Received Data Available: Is set when data in the Rx FIFO queue reaches a particular level (the trigger level can
be configured as 1, 4, 8 or 14) or if no character has been received for 4 character times.
Transmit FIFO Empty: set when the last character from the Tx FIFO is read and starts to be transmitted.
Receiver Line Status: set when one of the following occur (1) Parity Error - the character at the head of the
receive FIFO has been received with a parity error, (2) Overrun Error - the Rx FIFO is full and another character
has been received at the Receiver shift register, (3) Framing Error - the character at the head of the receive
FIFO does not have a valid stop bit and (4) Break Interrupt
– occurs when the RxD line has been held low for an
entire character.
Modem Status: Generated when the CTS (Clear To Send) input control line changes.
13.2 UART Application
The following example shows the UART connected to a 9-pin connector compatible with a PC. As the JN5142
device pins do not provide the RS232 line voltage, a level shifter is used.
