© NXP Laboratories UK 2012
JN-DS-JN5142 1v0
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The clock source for the Timer0 unit is fed from the 16MHz system clock. This clock passes to a 5-bit prescaler
where a value of 0 leaves the clock unmodified and other values divide it by 2
prescale
value. For example, a prescale
value of 2 applied to the 16MHz system clock source results in a timer clock of 4MHz.
The counter is optionally gated by a signal on the clock/gate input (TIM0CK_GT). If the gate function is selected,
then the counter is frozen when the clock/gate input is high.
An interrupt can be generated whenever the counter is equal to the value in either of the High or Low registers.
The internal Output Enable (OE) signal enables or disables the timer output.
Timer0 can be accessed, depending upon the configuration, on DIO8 to DIO10 or DIO2 to DIO4. PWM1,2,3 can be
accessed on DIO11 to DIO13 or DIO5 to DIO7. This is enabled under software control. Timer0 can be assigned to
its alternative location without moving the PWMs, and vice-versa. The following table details which DIO are used for
the PWM depending upon the configuration.
Signal
DIO Assignment
Standard pins
Alternative pins
TIM0CK_GT
31
18
TIM0CAP
32
19
TIM0OUT
33
26
PWM1
34
27
PWM2
36
28
PWM3
37
29
Table 5: Timer and PWM IO
If operating in timer mode it is not necessary to use any of the DIO pins, allowing the standard DIO functionality to be
available to the application.
11.1.1 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode, as used by PWM timers 1,2 and 3 and optionally by Timer0, allows the user to
specify an overall cycle time and pulse length within the cycle. The pulse can be generated either as a single shot or
as a train of pulses with a repetition rate determined by the cycle time.
In this mode, the cycle time and low periods of the PWM output signal can be set by the values of two independent
16-bit registers (Fall and Rise). The counter increments and its output is compared to the 16-bit Rise and Fall
registers. When the counter is equal to the Rise register, the PWM output is set to high; when the counter reaches
the Fall value, the output returns to low. In continuous mode, when the counter reaches the Fall value, it will reset
and the cycle repeats. The PWM waveform is available on PWM1,2,3 or TIM0OUT when the output driver is
enabled.
Rise
Fall
Figure 27: PWM Output Timings
11.1.2 Capture Mode
The capture mode can be used to measure the time between transitions of a signal applied to the capture input
(TIM0CAP). When the capture is started, on the next low-to-high transition of the captured signal, the count value is
stored in the Rise register, and on the following high-to-low transition, the counter value is stored in the Fall register.
The pulse width is the difference in counts in the two registers multiplied by the period of the prescaled clock. Upon
reading the capture registers the counter is stopped. The values in the High and Low registers will be updated
whenever there is a corresponding transition on the capture input, and the value stored will be relative to when the
