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Parameter
Description
PCI1 to PCI0 Access
Sets access between two different PCI buses. The Optimal
default is Disabled.
Method of Memory Detection
Sets how the system detects system memory. The Optimal
default is Auto & SPD.
DRAM Integrity Mode
Sets the type of memory checking. The Optimal default is
ECC Hardware.
DRAM Refresh Rate
Sets the interval between refresh signals to DRAM system
memory. The Optimal default is 15.6 us.
Memory Hole
Sets the area of memory that cannot be addressed on the
ISA bus. The Optimal default is Disabled.
SDRAM RAS# to CAS# delay
Sets the delay between RAS# and CAS# signals for
SDRAM memory. The Optimal default is 3 SCLKs.
SDRAM RAS# Precharge
Sets the length of RAS# precharge for SDRAM memory.
The Optimal default is 3 SCLKs.
Power Down SDRAM
Sets support for SDRAM memory power-down. The
Optimal default is Enabled.
ACPI Control Register
Sets support for the Advanced Configuration and Power
Interface (ACPI) control register. The Optimal default is
Disabled.
Gated Clock
Sets support for the gated clock. The Optimal default is
Disabled.
Graphics Aperture Size
Sets the amount of system memory that can be used by the
Accelerated Graphics Port (AGP). The Optimal default is
64 MB.
Search for MDA Resources
Sets a BIOS search for MDA resources. The Optimal
default is Yes.
AGP Multi-Trans Timer
Sets the AGP multi-trans timer. The Optimal default is 32.
AGP Low-Priority Timer
Sets the AGP low-priority timer. The Optimal default is 16.
AGP SERR
Sets support for the AGP SERR signal. The Optimal
default is Disabled.
AGP Parity Error Response
Sets support for AGP parity error response. The Optimal
default is Disabled.
8bit I/O Recovery Time
Sets the delay between consecutive 8-bit I/O operations.
The Optimal default is Disabled.
16bit I/O Recovery Time
Sets the delay between consecutive 16-bit I/O operations.
The Optimal default is Disabled.
PIIX4 SERR#
Sets support for the SERR# signal for the Intel PIIX4 chip.
The Optimal default is Disabled.
