Receiver Description
STEL-2176
10
User Manual
RECEIVER
OVERVIEW
The STEL-2176 is a complete subscriber-side cable
modem ASIC which integrates both the downstream
receiver and upstream transmitter functions. The
receiver includes a high performance 10-bit Analog-to-
Digital Converter (ADC) with a direct Intermediate
Frequency (IF) interface. The receiver also includes a
QAM demodulator and both ITU-T (J.83) Annex A and
Annex B Forward Error Correction (FEC). The
upstream transmitter includes a BPSK/QPSK/16QAM
modulator with highly flexible FEC and scrambling,
and a 10-bit low spurious digital to analog converter
(DAC) for direct synthesis of an upstream 5 to 65 MHz
signal. Both the receiver and transmitter are highly
flexible and programmable; the STEL-2176 Digital
Mod/Demod ASIC offers a solution to meet current
and evolving standards.
The input to the STEL-2176 receiver is an analog IF
signal of up to 50 MHz. Typically, the IF signal has 44
MHz center frequency with a 6 MHz bandwidth for
NTSC based systems, or a 36 MHz center frequency
with an 8 MHz bandwidth for PAL based systems. In
typical applications, the input signal is sampled by the
ADC at approximately 25 MHz for the 44 MHz IF, or at
approximately 29 MHz for the 36 MHz IF
This type of sub-sampling technique works by
intentionally undersampling the carrier frequency so
that aliased signal appears at a lower frequency. The
sampling rate is still high enough to capture all of the
modulation bandwidth without distortion. In the case
of a 44 MHz IF and a 25 MHz clock, the resulting digital
signal is centered at 6 MHz. In the case of a 36 MHz IF
and 29 MHz clock, the resulting digital signal is
centered at 7 MHz. For more information on sub-
sampling techniques, please see Stanford Telecom
Application Note A-117.
The digital samples from the ADC are downconverted
to baseband I and Q signals in the Digital Down
Converter (DDC) block. Since the RF tuner sections of a
cable modem may have large frequency errors, an
Automatic Frequency Control (AFC) block is used in
the STEL-2176 for coarse tuning of the DDC. This
allows rapid acquisition of the input signal even with
frequency errors of
±
200 kHz. Fine tuning of the DDC is
done using a carrier Phase-Lock Loop (PLL).
An Automatic Gain Control (AGC) function provides
two output signals to adjust the RF and IF analog gain
stages of circuitry external to the STEL-2176, so that the
ADC input is in the optimal range. The two outputs can
be programmed to create a sequential AGC system
which maximizes RF gain for improved receiver noise
figure. The two AGC outputs and the external gain
adjust blocks work together to maximize ADC
performance, but when large adjacent channels are
present, the power of the desired signal may change. A
second digital AGC tracks and adjusts the level of the
desired signal after the adjacent channel energy is
removed by filtering.
Following the DDC, a square root raised cosine Nyquist
filter eliminates adjacent channel signals, and performs
matched filtering to eliminate intersymbol interference.
The filter excess bandwidth or alpha is programmable
from 0.12 to 0.20. The Timing Recovery block finds the
exact location in the center of each symbol using a
special low-jitter discriminator. These values are fed to
the Adaptive Channel Equalizer.
An Adaptive Channel Equalizer (ACE) compensates for
any multipath distortion on the input signal introduced
in the channel. The equalizer uses one sample per
symbol (T spaced taps). The output of the equalizer is
baseband I and Q signals with carrier frequency and
phase errors, symbol timing errors, gain errors, and
multipath effects removed.
The Demapper takes the baseband I and Q signals
representing the QAM symbols, and translates each
symbol back into a series of binary values based on one
of the selectable constellation maps.
Following the Demapper is the Forward Error
Correction (FEC) system. This programmable system
supports both the ITU-T (J.83) Annex A (see page 14)
and Annex B (see page 16) standards. In general, both
FEC systems employ Reed Solomon Decoders, Frame
Sync circuits that determine the FEC code block
boundaries, and a De-Interleaver. Interleaving is used
in the FEC standards to improve performance when the
channel contains bursty noise. Since the transmitter
Interleaver spreads the data over a large time, when the
receiver performs the matched operation to the
Interleaver in order to bring the data back into the
correct time sequence, any burst errors appear to be
spread out in time. This helps makes these errors
