Intel® SRMK2 Internet Server Technical Product Specification
86
Table 58: PCI bus error control bits
Location
Function Bit
Description
Value
CNB30LE
04h-05h
PCICR
8
SERR# enable
1 = enable, 0 = disable
6
PERR# enable
1 = enable, 0 = disable
CNB30LE
06h-07h
PCISR
15
Detected Parity Error
1 = error, 0 = OK
14
Signaled System Error
1 = error, 0 = OK
13
Received Master Abort
1 = error, 0 = OK
12
Received Target Abort Status
1 = error, 0 = OK
8
Data Parity Detected
1 = error, 0 = OK
CNB30LE
46h
ERRCMD
7
Enable SERR# on Received Target Abort
1 = enable, 0 = disable
6
Enable SERR# on Transmitted Data Parity Error
1 = enable, 0 = disable
5
Enable SERR# on Received Data Parity Error
1 = enable, 0 = disable
4
Enable SERR# on Address Parity Error
1 = enable, 0 = disable
3
Enable PERR# on Received Data Parity Error
1 = enable, 0 = disable
2
Enable SERR# on ECC Uncorrectable Error
1 = enable, 0 = disable
1
Enable SALERT on ECC Correctable Error
1 = enable, 0 = disable
0
Enable SERR# on Received Master Abort
1 = enable, 0 = disable
CNB30LE
47h
ERRSTS
6
PCI Transmitted Data Parity Error
1 = error, 0 = OK
5
PCI Received Data Parity Error
1 = error, 0 = OK
4
PCI Address Parity Error
1 = error, 0 = OK
2
DRAM Uncorrectable Error
1 = error, 0 = OK
1
DRAM Correctable Error
1 = error, 0 = OK
0
Shutdown Cycle Detected
1 = error, 0 = OK
9.3.2 Processor Bus Error
The CNB30LE does not report processor bus AERR# and BERR# error signals to the system.
(AERR# indicates an address parity error and BERR# indicates an unrecoverable processor bus
error.) Therefore, the system SMM handler does not log and report these types of errors to the
OS.
Содержание SRMK2 - Server Platform - 0 MB RAM
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