Intel SRMK2 - Server Platform - 0 MB RAM, Технические характеристики

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Intel® SRMK2 Internet Server Technical Product Specification 85
9.2.1.3 SMI Handler
The SMI handler preprocesses all system errors, even those that are normally considered to
generate an NMI. The SMI handler is responsible for properly detecting the error type, logging it
to the appropriate error log, and passing the error on to the OS if required.
9.3 ISA Bus Error
ISA bus errors generate an NMI, triggered by a memory error or IOCHK# assertion on the ISA
bus. The SRMK2 always uses ECC memory, so it emulates the ISA memory parity error as an
uncorrectable ECC memory error. For other system fatal errors generated by the PCI or
processor bus, the SMI handler can emulate a memory parity error to pass control to the NMI
handler. An I/O register at 61h (System Control port B) is defined that controls and indicates the
errors. The NMI can be disable d using the RTC Index port bit 7 (I/O port 70h). The following
tables show the action taken by each error handler, and control bits associated with the error.
Table 55: Error handler action on ISA bus error
Handler Action
BIOS NMI Display an error message, and halt the system.
OS NMI Log the error and gracefully shut down the system.
BIOS SMI Log the event(s).
Table 56: ISA bus error control bits
Location Function Bit(s) Description Value
I/O 61h System Control 7 Memory parity check error flag (RO) 1 = error, 0 = OK
Port B
6 Channel check (IOCHK#) error flag (RO)
5::4 Reserved
3 Channel check enable (RW) 1 = enable, 0 = disable
2 Parity check enable (RW) (system board
error enable)
1::0 Reserved
9.3.1.1 PCI Bus Error
The PCI bus defines two error pins, PERR# and SERR#, for reporting PCI parity errors and
system errors, respectively. In the case of PERR#, the PCI bus master has the option to retry the
offending transaction, or to report it using SERR#. All other PCI-related errors are reported
directly by SERR#. SERR# can be routed to NMI. In the SRMK2 platform, PAC is the device
that reports errors on PCI #1 using SERR#. All the PCI-to-PCI bridges are configured so they
generate SERR# on the primary interface whenever there is SERR# on the secondary side. The
same is true for PERR#. The following tables show the action taken by each error handler, and
the control bits associated with this error.
Table 57: Error handler action on PCI bus error
Handler Action
BIOS NMI Halt the system and disable NMI
OS NMI Log the error and shut down the system
BIOS SMI Log PCI errors