Intel SRMK2 - Server Platform - 0 MB RAM, Технические характеристики

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Intel® SRMK2 Internet Server Technical Product Specification 84
9 Error Handling, Messages & Beep Codes
This section defines how errors are handled by the system BIOS on the SRMK2 pla tform. It
describes the role of the BIOS in error handling and the interaction between the BIOS and
platform hardware as far as error handling is concerned. In addition, error-logging techniques are
described, and beep codes for errors are defined.
9.1 Error Sources and Types
One of the major requirements of server management is to correctly and consistently handle
system errors. System errors on SRMK2 can be categorized as follows:
•
ISA bus
•
PCI bus
•
Memory single and multi-bit errors
•
Sensors
•
Processor internal error, thermal trip error, temperatures and voltages, GTL voltage
levels
The BIOS cannot detect errors on the processor bus because the CNB30LE does not monitor
these. ISA and PCI bus errors can be further classified as ‘standard bus’ errors, which have a
standard register interface across all platforms. All other errors, such as processor and ECC
errors, are referred to as ‘product-specific’ errors, which require special consideration depending
upon the system configuration. Product-specific errors can be emulated as standard bus errors, if
specific routing of certain hardware signals, as documented in this section, is followed. This
emulation is important to both OS and BIOS NMI handlers, which have no knowledge of product-
specific errors, but need to recover and shut down the system gracefully.
9.2 Error Handlers
The BIOS has an NMI handler that gets invoked when an NMI occurs in POST. Generally, the
OS traps the NMI and does not pass it on to the BIOS NMI handler. Therefore, the BIOS NMI
handler is rarely invoked in a real operating environment. The SMI handler cannot be bypassed
by the OS, and is used to handle and log system-level events that are not visible to the OS.
9.2.1.1 BIOS NMI Handler
To maintain DOS compatibility, the BIOS NMI handler only processes enabled standard bus
errors, such as ISA Parity check or IOCHK# errors. It displays an error message, issues a beep
signal, and halts. It disables NMI using bit 7 of I/O port 70h (RTC Index Port) on the occurrence
of an unknown or spurious NMI. This can cause unusual side effects because it allows a spurious
NMI to block a subsequent valid NMI.
9.2.1.2 OS NMI handler
The OS NMI handler processes standard bus errors at the OS level. Most OS NMI handler
implementations are not product specific and behave in a manner similar to a BIOS NMI handler.
It is the responsibility of the BIOS SMI handler to present platform-specific errors, such as multi-
bit ECC errors, as one of the standard bus errors, like parity error, to the OS NMI handler.