Intel SRMK2 - Server Platform - 0 MB RAM, Технические характеристики

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Intel® SRMK2 Internet Server Technical Product Specification 65
all the operating systems have migrated to MPS version 1.4, MPS version 1.1 is no
longer supported. The MP Configuration Table contains the following entries:
•
MP table header
•
Processor entries
• PCI bus entries
•
I/O APIC entries
•
I/O interrupt entries
•
Local interrupt entries
• System address space mapping entries
•
Bus hierarchy descriptor
•
Compatibility bus address space modifier entries
Note that some I/O interrupt entries in the MPS table describe a direct connection from
each PCI device to the I/O APICs. This is different from previous Dual Processor
platforms. In previous platforms, the PCI interrupts were represented in terms of their
equivalent ISA IRQ’s in the MPS table by default, and there was a setup switch to
control the representation.
The setup switch is no longer supported because all of the operating systems now
correctly support the PCI interrupts. Not having a configuration option provides more
flexibility in baseboard design. Describing direct PCI interrupt connections permits the
operating system and the BIOS to minimize interrupt sharing between PCI devices, and
improves interrupt latencies. All SMP operating systems and associated drivers must
be able to support an interrupt vector larger than 16 for it to work on the SRMK2
motherboard.
7.3.1.2.2 Multiple processor support
Pentium
®
III processors have a protocol based on microcode-MP initialization. On reset,
the Pentium
®
III processors compete to become the BootStrap Processor (BSP). If a
serious error is detected during the Built-In Self-Tests (BIST), that processor does not
participate in the initialization protocol. A single processor that successfully passes
BIST is automatically selected by the hardware as the BSP. This processor starts
executing from the reset vector (F000:FFF0h). A processor that does not perform the
role of BSP is referred to as an Application Processor (AP). The BSP is responsible
for executing POST and preparing the machine to boot the OS.
The SRMK2 BIOS performs several other tasks in addition to those required for MPS
support, as described in
MP Specifications , Revision 1.4. These tasks are part of the
fault resilient booting algorithm. At the time of booting, the system is in virtual wire
mode and only the BSP is programmed to accept local interrupts (INTR driven by the
PIC and NMI). As a part of the boot process, the BSP wakes each AP. When
woken, an AP programs its memory type range registers (MTRRs) so they are identical
to those of the BSP. All APs execute a halt instruction with their local interrupts
disabled. The SMM handler, expects all the system processors to respond to an SMI.
To ensure that an AP can respond to an IPI, any agent that wakes an AP must ensure
that the AP is left in the halt state, not the “wait for startup IPI” state. The waking
agent must also ensure that the code segment containing the halt code executed by an