Intel SRMK2 - Server Platform - 0 MB RAM, Технические характеристики, Страница: 69 / 115

Intel® SRMK2 Internet Server Technical Product Specification 69
7.3.2.5 Chipset Performance Optimization
The BIOS detects the system configuration (such as board ID, chipset stepping, and processor
stepping) and optimizes the chipset for the best performance. The BIOS no longer supports a 1
MB hole at the 15-16 MB memory region.
7.3.3 Reliability Features
The BIOS supports several features to create a robust computing environment including:
•
ECC memory and defective DIMM handling
•
Logging of critical events
•
CMOS default override
•
Fault-Resilient Booting (FRB)
Also see Section 9 for more information on error handling and critical event logging.
7.3.3.1 Defective DIMM Detection and Remapping
The ECC memory subsystem on the SRMK2 is able to detect single -bit errors (SBE) and certain
multi-bit errors (MBE) during reads from and writes to system DRAM. Single -bit errors can be
detected and corrected. Certain patterns of MBEs can be detected but cannot be corrected,
whereas other types of MBEs cannot be detected.
During POST memory testing, detection of single -bit and multi-bit errors in DRAM banks is
enabled. Repeat errors are avoided by reducing the usable memory in that bank so the byte
containing the hard error is no longer accessible. This is done automatically by the BIOS during
POST and does not require any user intervention. The BIOS logs the errors in the nonvolatile
system event log. The BIOS detects the speed of individual DIMMs and disables a DIMM that is
slower than what the hardware requires while displaying a warning message.
7.3.3.2 Memory Configuration Algorithm
The algorithm for determining memory configuration is as follows:
1) If there is no DIMM population or the DIMMs are defective or have the wrong speed then
the BIOS sounds a beep code error and POST is terminated. At least 4 MB of good memory
is required for POST to start up and each memory bank is individually probed for the size of
installed DIMMs. After the BIOS detects the speed and type of the SDRAM it then
programs the chipset accordingly. If the bank does not match one of the allowable
configurations, BIOS reports the error with an error message. EDO memory is not physically
supported due to the memory socket used on the serverboard. The BIOS will automatically
shut off all ECC capability for the system if non-ECC memory is detected. All configuration
data for the memory DIMMs is gathered by the BIOS from the SPD or EEPROM on the
DIMM which is done via the SMBus interface on the OSB4.
2) If the BIOS disables or resizes a bank, an error message is displayed with the number of the
failed memory. Another message informs the user that the amount of usable memory in that
bank is being reduced to eliminate the failing location. Eliminating hard errors in this way
during POST is done as a precaution to prevent an SBE from becoming an MBE after the
system has booted and to prevent SBEs from being detected and logged each time the failed
location(s) are accessed. This is recorded in the SEL (System Event Log) at both POST
time as well as runtime with an SMI.