Intel® SRMK2 Internet Server Technical Product Specification
44
Table 31: IDE connector – J9 Primary
Pin Signal Name
Pin Signal Name
1
Reset IDE
2
Ground
3
Data 7
4
Data 8
5
Data 6
6
Data 9
7
Data 5
8
Data 10
9
Data 4
10
Data 11
11
Data 3
12
Data 12
13
Data 2
14
Data 13
15
Data 1
16
Data 14
17
Data 0
18
Data 15
19
Ground
20
Key (NC)
21
DDRQ0 [DDRQ1]
22
Ground
23
DIOW#
24
Ground
25
DIOR#
26
Ground
27
DRDY
28
CSEL (Cable Select pull-down)
29
DDAK0# [DDAK1#]
30
Ground
31
IRQ 14 [IRQ 15]
32
Reserved
33
IDE_A1 (Address 1)
34
Reserved
35
IDE_A0 (Address 0)
36
IDE_A2
37
IDE_CS1#
38
IDE_CS3#
39
IDE_ACT#
40
Ground
Note: Signal names in brackets ([ ]) are for the secondary IDE connector.
3.17.2.2
Wake Headers and Power
Figure 15 shows the locations of the Wake headers and power connectors.
A
B
C
A
Wake on LAN connector
C Power supply connector
B
Wake on Ring connector
Figure 15: Hardware management and power connectors
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