Intel M50FCP1UR, Руководство пользователя

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Intel® Server System M50FCP1UR System Integration and Service Guide
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Upper nibble bits = 1010b = A h; Lower nibble bits = 1100b = C h; the two Hex Nibble values are combined to
create a single AC h POST Progress Code.
D.1 Early POST Memory Initialization MRC Diagnostic Codes
Memory initialization at the beginning of POST includes multiple functions: discovery, channel training,
validation that the DIMM population is acceptable and functional, initialization of the IMC and other
hardware settings, and initialization of applicable RAS configurations.
The MRC progress codes are displayed to the diagnostic LEDs that show the execution point in the MRC
operational path at each step.
Table 9. MRC Progress Codes
MRC
Progress
Code
(Hex)
Upper Nibble Lower Nibble
Description
8h 4h 2h 1h 8h 4h 2h 1h
73 0 1 1 1 0 0 1 1 NVRAM sync.
7E 0 1 1 1 1 1 1 0 MRC internal sync.
B0 1 0 1 1 0 0 0 0 Detect DIMM population
B1 1 0 1 1 0 0 0 1 Set DDR5 frequency
B2 1 0 1 1 0 0 1 0 Gather remaining SPD data
B3 1 0 1 1 0 0 1 1 Program registers on the memory controller level
B4 1 0 1 1 0 1 0 0 Evaluate RAS modes and save rank information
B5 1 0 1 1 0 1 0 1 Program registers on the channel level
B6 1 0 1 1 0 1 1 0 Perform the JEDEC defined initialization sequence
B7 1 0 1 1 0 1 1 1 Train DDR5 ranks
0 0 0 0 0 0 0 0 0 Train DDR5 channels: Receive enable training
3 0 0 0 0 0 0 1 1 Train DDR5 channels: Read DQ/DQS training
4 0 0 0 0 0 1 0 0 Train DDR5 channels: Write DQ/DQS training
11 0 0 0 1 0 0 0 1 Train DDR5 channels: End of channel training.
77 0 1 1 1 0 1 1 1 Train DDR5 channels: Write leveling training.
B8 1 0 1 1 1 0 0 0 Initialize CLTT/OLTT
B9 1 0 1 1 1 0 0 1 Hardware memory test and initialization
BA 1 0 1 1 1 0 1 0 Execute software memory initialization
BB 1 0 1 1 1 0 1 1 Program memory map and interleaving
BC 1 0 1 1 1 1 0 0 Program RAS configuration
BE 1 0 1 1 1 1 1 0 Execute BSSA RMT
BF 1 0 1 1 1 1 1 1 MRC is done
Should a major memory initialization error occur, preventing the system from booting with data integrity, a
beep code is generated, the MRC displays a fatal error code on the diagnostic LEDs, and a system halt
command is executed. Fatal MRC error halts do not change the state of the system status LED and they do
not get logged as SEL events. Table 10 l ists all MRC fatal errors that are displayed to the diagnostic LEDs.
Note: Fatal MRC errors display POST error codes that may be the same as BIOS POST progress codes
displayed later in the POST process. The fatal MRC codes can be distinguished from the BIOS POST progress
codes by the accompanying memory failure beep code of three long beeps as identified in Table 13.