Intel M20NTP1UR, Руководство по системной интеграции и обслуживанию

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Intel® Server System M20NTP1UR - System Integration and Service Guide
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Status Code Description
SEC Error Codes
0x0C – 0x0D Reserved for future AMI SEC error codes
0x0E Microcode not found
0x0F Microcode not found
SEC Beep Codes
• None
Pre-EFI Initialization (PEI) Phase
Status Code Description
Progress Codes
0x10 PEI Core is started
0x11 Pre-memory CPU initialization is started
0x12 Pre-memory CPU initialization (CPU module specific)
0x13 Pre-memory CPU initialization (CPU module specific)
0x14 Pre-memory CPU initialization (CPU module specific)
0x15 Pre-memory North Bridge initialization is started
0x16 Pre-Memory North Bridge initialization (North Bridge module specific)
0x17 Pre-memory North Bridge initialization (North Bridge module specific)
0x18 Pre-Memory North Bridge initialization (North Bridge module specific)
0x19 Pre-memory South Bridge initialization is started
0x1A Pre-Memory South Bridge initialization (South Bridge module specific)
0x1B Pre-memory South Bridge initialization (South Bridge module specific)
0x1C Pre-Memory South Bridge initialization (South Bridge module specific)
0x1D – 0x2A OEM pre-memory initialization codes
0x2B Memory initialization. Serial Presence Detect (SPD) data reading
0x2C Memory initialization. Memory presence detection
0x2D Memory initialization. Programming memory timing information
0x2E Memory initialization. Configuring memory
0x2F Memory initialization (other)
0x30 Reserved for ASL (see ASL Status Codes section below)
0x31 Memory Installed
0x32 CPU post-memory initialization is started
0x33 CPU post-memory initialization. Cache initialization
0x34 CPU post-memory initialization. Application Processor(s) (AP) initialization
0x35 CPU post-memory initialization. Boot Strap Processor (BSP) selection
0x36 CPU post-memory initialization. System Management Mode(SMM) initialization
0x37 Post-Memory North Bridge initialization is started
0x38 Post-Memory North Bridge initialization (North Bridge module specific)
0x39 Post-Memory North Bridge initialization (North Bridge module specific)
0x3A Post-Memory North Bridge initialization (North Bridge module specific)
0x3B Post-Memory South Bridge initialization is started
0x3C Post-Memory South Bridge initialization (South Bridge module specific)
0x3D Post-Memory South Bridge initialization (South Bridge module specific)