ICS ELECTRONICS 9099, Инструкция по эксплуатации

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3.3 488.2 STATUS REPORTING STRUCTURE
The 9099 has multiple copies of the expanded IEEE-488.2 status reporting
structure shown in Figure 3-1. The expanded status reporting structure conforms
to the SCPI 1994.0 Specification and builds on the IEEE 488.2 Standard Status
Reporting Structure by adding the Questionable and Operation registers. The
Event and Status registers are controlled and queried with the IEEE-488.2 com-
mon commands. The Status Byte Register may also be read by serial polling
the card. The Questionable and Operation registers are controlled and queried
with SCPI commands. The Modbus Error register is read and cleared with the
Modbus E? query. The register readings are the sum of the binary weights of
the bits whose value is a '1'.
Instead of asserting the GPIB SRQ line, VXI-11.3 Instruments generate a
Service Request message, device_intr_SRQ, when the RQS bit in the Status
Byte Register becomes true. Service Requests (SRQs) are sent through the
Interrupt Channel (if one has been setup) to alert the client that an event has
occurred and/or that the device needs service. Service Request generation is
a multilevel function and is determined by the occurrence of an event that has
its corresponding enable bit set to '1'. The outputs from the event registers are
summarized in separate bits in the Status Byte Register. The Event registers
and the Output Queue are cleared when read or by the *CLS command.
Service Requests are not automatically sent to the user when using raw socket
or the USB bus.
3.3.1 Event Registers
An event register captures 0 to 1 transitions in its associated condition reg-
ister or in the standard event register. An event bit becomes TRUE (1) when
the associated condition bit makes a logical 0 to 1 transition. Once an event
bit is set it is held until the event register is read or cleared with the *CLS
command.
Each event register contains eight or sixteen bits. When the register is read,
its response is a decimal number that is the sum of the binary bit weights of
the bits that are logical 1s.
e.g. 23 decimal = 0001 0111 or 0000 0000 0001 0111 binary
Each event register bit has a corresponding enable bit. The enabling bits are
ANDed with the state of the event bits to create the summary condition in the