ICS ELECTRONICS 9099, Инструкция по эксплуатации

Страница: 117 / 178

A-5
A1
A1.2 IEEE 488.2 STANDARD
A1.2.1 IEEE 488.2 Message Formats
The IEEE 488.2 Standard was established in 1987 to standardize message
protocols, status reporting and define a set of common commands for use on
the IEEE 488 bus. A VXI-11.3 TCP/IP-IEEE 488.2 Instrument Interface and
its associated instrument follows all the requirements in IEEE 488.2 except
where the difference between the TCP/IP-IEEE 488.2 Instrument Interface and
IEEE 488.1 requires clarification.
IEEE 488.2 devices are supposed to receive messages in a more flexible man-
ner than they send. A message sent from GPIB controller to GPIB device is
called: PROGRAM MESSAGE. A message sent from device to controller is
called: RESPONSE MESSAGE. As part of the protocol standardization the
following rules were generated:
(;) Semicolons are used to separate messages.
(:) Colons are used to separate command words.
(,) Commas are used to separate data fields.
<nl> Line feed and/or EOI on last character terminates a
'program message'. Line feed (ASCII 10) and EOI terminates
a RESPONSE MESSAGE.
(*) Asterisk defines a 488.2 common command.
(?) Ends a query where a reply is expected.
A1.2.2 IEEE 488.2 Reporting Structure
With IEEE 488.2, status reporting was enhanced from the simple serial poll
response byte in IEEE 488.1 to the multiple register concept shown in Figure
A-1. The IEEE 488.2 Standard standardized the bit assignments in the Status
Byte Register, added eight more bits of information in the Event Status Register
and introduced the concept of summary bits reporting to the Status Byte Reg-
ister. The Status and Event registers have enabling registers that can control
the generation of their summary reporting bits and ultimately SRQ generation.
Each 488.2 device must implement a Status Byte Register, a Standard Event
Status Register and an Output Message Queue as a minimum status reporting
structure. A device may include any number of additional condition registers,
event registers and enabling registers providing they follow the model shown
in Figure A-1.