HP 64783A, Руководство пользователя

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for systems designed to work with small buffer mode, the emulator buffers all
signals from the processor to the target connector. Most of the signals are buffered
in ABT logic family parts. These parts are chosen to provide high speed and high
current capability while keeping slew rates to an acceptable level for small buffer
mode systems. Some control signals are buffered in PALs which have significantly
less drive capability than the processor in large mode.
Examine the DC specifications of the emulator to evaluate their differences from
processor specifications. Again, you can refer to the equivalent circuit diagrams in
this chapter for exact details. Because the emulator does not behave exactly like
the processor, you may need to examine signal quality and take appropriate steps to
compensate for differences.
The BCLK clock is the most important signal to the emulator because all system
timing is derived from this signal. The BCLK clock signal must have clean edges;
the duty cycle of this clock is not particularly important. The emulator regenerates
an internal BCLK from this signal with a 50% duty cycle. All timing is referenced
from the rising edge of BCLK. The PCLK clock is also internally regenerated;
therefore, the emulator is not sensitive to this signal.
Both the BCLK and PCLK signals are terminated on the emulator. The
terminations are placed on these signals, even though the emulator causes only a
short electrical stub, so that accessories such as the flexible cable can be used to
connect the emulator probe to your target system. The terminations on these
signals can interact with terminations on your target system. Refer to the
equivalent circuits in this chapter and adjust terminations in your target system for
best results.
The emulator uses power from the target system to operate the emulation processor
and some pullup resistors. Target power is sensed to make sure the emulator does
not drive the target system until it is powered up. In addition, the power detection
circuit delays release of processor reset for 50 ms after power is in specification to
allow the clock circuits to synchronize. Because of the protections designed into
the emulator, always power on the emulator before the target system and power off
the emulator after the target system.
Chapter 18: Connecting the Emulator to a Target System
Plugging The Emulator Into A Target System
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