HP 64783A, Руководство пользователя

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One thing to keep in mind is that the emulator does not trace alternate bus master
cycles while it is reset.
If any bus cycles were executed before the reset occurred, then something caused
the target system to reassert the reset condition. Usually, this is caused by some
type of fault which is detected by the system. This may result from access to a
certain address range or because of a watchdog timeout. Refer to "Interpreting the
Trace List", later in this chapter, to help you understand what caused the reset.
If the prompt is "b>", and there are no cycles in the trace list, the processor never
attempted to run any bus cycles even if other indications show it should have. This
could indicate problems with power, clock, or signal transitions, especially the reset
signal. Check power supply voltage levels. Make sure the power up is monotonic.
Check clock quality. Check that the reset signal meets its required assertion time
after power up and clock stabilization. Check signal quality on the reset signal,
especially the signal transitions.
If some cycles were captured in the trace list, but no cycles are occuring now, check
for setup and hold violations on the processor strobes. All MC68040 signals,
except the interrupt lines and reset signal, are synchronous to the clock and have to
be valid for all rising edges of BCLK. Check timing inputs to the emulator, such as
TA, TEA, and TBI , for setup and hold violations. The "b>" prompt is not a normal
condition for the processor when you find no functional reason. It usually indicates
that the processor has malfunctioned.
One possible cause of a "b>" prompt is the processor missing the end-of-cycle
indication during the cycle of an alternate bus master. The processor monitors the
TS signal during alternate bus master activity to see if it needs to intervene in the
cycle (snooping). If the processor sees a TS signal but misses the corresponding
TA signal, the processor may hang, waiting for this bus cycle to complete, even
though the bus was granted to the MC68040 and released.
If bus cycles are occuring, then the "b>" prompt only indicates that bus cycles are
infrequent. A type of system that would exhibit this behavior would be an
interrupt-driven system. When done processing an interrupt, the system could
execute a STOP instruction to wait for the next interrupt. If the interrupts were
infrequent a "b>" prompt would be displayed.
If the prompt is "w>", the emulator has stopped in the middle of a bus cycle. Get
the emulation status; it will tell you the address and the type of cycle.
Chapter 18: Connecting the Emulator to a Target System
Verifying Operation Of The Emulator In Your Target System
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