HP 64783A, Руководство пользователя

Страница: 655 / 816

A basic MC68040 bus cycle starts with the transfer start signal, TS. The TS signal
pulses low for about one clock cycle. Another signal, transfer in progress TIP stays
low throughout the cycle, but is not necessarily deasserted between cycles. The end
of the cycle occurs when the processor samples a transfer acknowledge TA or a
transfer error acknowledge TEA or both on the rising edge of the clock. Because of
the nature of these signals, most systems are synchronous to the clock. The typical
system will sample TS on the rising clock edge and then generate a TA signal an
intregal number of clocks later. Wait states are added to a cycle by delaying when
the TA is asserted.
If the emulator is configured for wait states (BCLK >25 MHz), then a compatibility
problem with the emulator may be stalling the processor.
w>cf
cf cache=en
cf mmu=en
cf mon=none
cf rrt=dis
cf ti=en
cf wait=en <- configuration for wait states
w>
The emulator requires at least one wait state in all bus cycles when it is configured
as above. The emulator does not add this wait state, but will not accept a TA from
the target system until after a wait state has been added. If TA is asserted by the
target system during the wait state period and is then deasserted before the emulator
allows termination, the bus cycle will never complete.
This particular example can be easily duplicated on the demo board by configuring
for wait states and interlocking memory to the demo board.
cf wait=en
map 0..0ff eram lock
r rst
If there is no functional reason why the bus cycle would not complete, check the
timing relationships between the various bus cycle control signals. Probably the
first measurement you will want to make is to see if the setup time of TA to BCLK
is within the emulator specification.
If there are no cycles in the trace list, then the processor stopped during the first bus
cycle. In this case, it is pretty easy to set up the trace using TS as the trigger
because the cycle of interest is the first cycle. If there are only a few cycles in the
trace list, the same technique can be used if the oscilloscope or timing analyzer has
enough depth.
Chapter 18: Connecting the Emulator to a Target System
Verifying Operation Of The Emulator In Your Target System
625