k
2 - 20
GRUNDIG Service
Descriptions
GDV 100 D
Pin
Name
I/O
Function
125-127
A[2:0]
I
Address
42
ACLK
I
Audio Clock
70
AGND
I
Analog ground
79
AREQ
O
Audio Data Request
41
AS
I
Address Strobe
121
ASDATA
O
Audio Serial Data Line
80
AVALID
I
Audio Data Valid
68
AVDD
I
Analog Power
71, 73-78, 83-84
BA[8:0]
O
DRAM Address
2
BCLK
O
Serial DAC Bit Clock
138-139, 36-38,
43-45, 48-50, 52-61
BD[63:0]
I/O
DRAM Data
118
BLANK
O
Composite Video Blanking
64
CAS
O
DRAM Column Address Select
123
CREF
O
Chroma Reference
132
CS
I
Chip Select
103-110
D[7:0]
I/O
User Data Bus
121
ERROR
I
Serial Error
96
HS
I/O
Horizontal Sync
137
INTR
O
Interrupt
69
LP2
I/O
Loop Filter Connection
1
LRCLK
O
Serial DAC L/R Clock
66
OE
O
DRAM Output Enable
159
OSD
I/O
OSD Active
133
READ
I
Read
89-95
PD[7:0]
O
Pixel Data
65
RAS
O
DRAM Row Address Select
102
RESET
I
Reset
82
SCLKI
I
Serial Clock In
114
SERI
I
Serial Data Input
87
SYSCLK
I
System Clock
111
VREQ
O
Video Data Request
135
VVALID
I
Video Data Valid
97
VS
I/O
Vertical Sync
134
WAIT
O
Data Wait
67
WE
O
DRAM Write
12, 28, 39, 47, 51, 63,
85, 98, 99, 101, 113,
122, 136, 144, 153
GND
–
Ground
11, 20, 27, 40, 46, 62,
72, 86, 112, 129, 143,
152, 160
VDD
–
Power Supply
81, 100, 119, 128, 130,
131, 115, 116, 117, 120 NC
–
Not connected
7303
125
126
127
42
70
79
41
121
80
68
84
83
78
77
76
75
74
73
71
2
19
18
17
16
15
14
13
10
9
8
7
6
5
4
3
158
157
156
155
154
151
150
149
148
147
146
145
142
141
140
139
138
118
64
123
132
103
104
105
106
107
108
109
110
124
98
39
136
122
99
101
12
28
47
63
85
113
144
153
51
96
137
69
1
130
128
119
100
81
131
66
159
88
89
90
91
92
93
94
95
65
133
120
117
116
115
102
82
114
87
72
40
160
129
11
27
46
62
86
112
143
152
20
111
97
135
134
67
L64005
VIDEO INTERFACE
INTERFACE
AUDIO
WAITN
RESETN
NC1
NC2
NC3
INTRN
NC4
NC5
NC6
RES1
RES2
RES3
RES4
READ
A0
A1
A2
D0
D1
D5
D6
ASN
D7
CSN
D4
D2
D3
CLK_GEN.
MPEG2 IN
VVALID
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
OSD
VS
HS
CREF
BLANK
BCLK
LRCLF
ASDATA
ACLK
BD63
BD62
BD61
BD60
BD59
BD58
BD57
BD56
BD55
BD54
BD53
BD52
BD51
BD50
BD49
BD48
BD47
BD46
BD45
BD44
BD43
BD42
BD41
BD40
BD39
BD38
BD37
BD36
BD35
BD34
BD33
BD32
MEMORY I/F
HOST I/F
SYSCLK
AREQN
AVALID
ERRORN
SCLK1
SER1
VREQN
GND4
VDD5
GND5
VDD6
GND6
VDD7
GND7
VDD8
GND8
VDD9
GND9
VDD10
GND10
VDD11
GND11
VDD12
GND12
VDD13
GND13
GND14
GND15
AVDD
AGND
LP2
WEN
RASN
OEN
CASN
BA0
BA1
BA2
BA3
BA4
BA5
BA6
BA7
BA8
VDD1
GND1
VDD2
GND2
VDD3
GND3
VDD4
MPEG AVG DECODER
INTEGRATED
LSI
61
50
49
48
45
44
43
38
37
36
35
60
34
33
32
31
30
29
26
25
24
23
59
22
21
58
57
56
55
54
53
52
BD14
BD13
BD12
BD11
BD10
BD9
BD16
BD8
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
BD15
BD19
BD20
BD21
BD22
BD23
BD24
BD25
BD26
BD27
BD28
BD18
BD29
BD30
BD31
BD17
IC7303
L64005: MPEG-2 Audio/Video Decoder
Function Overview
The L64005 is a main level, main profile MPEG-2 decoder.
It performs MPEG-2 system layer decoding of the Pack and PES layer.
The decoder outputs video through an 8-bit interface clocked at the
device clock (27MHz).
Features
– Provides a highly integrated, studio quality MPEG-2 audio/video
decoder solution.
– Decodes an MPEG-2 bit stream, including the MPEG-2 PES layer.
– Decodes an MPEG-1 bit stream as defined in ISO IS 11172,
including the MPEG-1 system layer.
– Decodes dual channel MPEG audio, LAYER 1 and 2 (MUSICAM),
with additional support for low sample rate coding and data rates
from 8 to 448 kbps.
– Operates at image sizes up to CCIR 601 resolution 720 x 480 pixels
@ 30 fps for NTSC and 720 x 576 @ 25 fps for PAL.
– Supports master or slave video timing operation.
– Integrates post processing filters for image resizing.
– Implements 3:2 pulldown and various wide screen modes, including
16:9 mode.
– Supports up to 20Mbit/s serial, or 40Mbit/s parallel, input channel
data rate.
– Supports 1-bit serial or 8-bit parallel input data formats through
external microcontroller.
– Provides 8-bit Y/C output data format in interlaced or progressive
scanned mode.
– Provides a complete on-chip channel buffer and display buffer
controls.
– Includes programmable display management.
– Interfaces to an inexpensive 8 bit microcontroller for initialization,
testing and status monitoring.
– Supports downloadable quantization tables through bitstream.
– Provides programmable channel buffer and display buffer size.
– Connects directly to commodity DRAMs.
– 16Mbits of DRAM, from four 4-Mbit regular DRAMs or one 16-Mbit
SDRAM, is required for CCIR601 resolution.
– Maintains display of images during channel errors with error con-
cealment.
– Provides selectable error concealment in audio decoder.
– Requires no external microcode or external logic.
– Optimizes input/output interfaces for glueless integration into con-
sumer video system to provide a cost effective solution.
– Operates from a single 27MHz clock, with optional additional audio
sample clock input.
