Grundig GDV 100 D, Руководство по обслуживанию

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k
2 - 14 GRUNDIG Service
Descriptions GDV 100 D
Digital Board
IC7100
DRC: DRAM Controller
Function Overview
The DRAM-Controller (DRC) interfaces between the CPU (IC7111)
and 1 or more DRAMs (IC7102,IC7103). In addition it provides 4 chip-
select lines (not used). Basically, when the CPU wants to read/write
data from/into the DRAM, the DRC merely provides the DRAMs with
the appropriate control-signals (RAS, CAS, WE, OE) and addresses,
while the databus is connected directly between the DRAMs and the
CPU. To maintain the data integrity in the DRAMs, the DRC (almost)
periodically refreshes the DRAMs in bursts of 8 Cas-Before-Ras
cycles.
DRAM
CONTROLLER
7100
9
10
11
12
15
16
17
20
21
25
33
26
28
29
43
36
37
38
39
40
41
4
7
6
30
32
31
67
66
2
64
3
59
49
13
14
58
57
55
24
47
45
54
51
50
63
22
48
62
65
56
23
46
44
18 34 52 68
19 35 53 61 1 8 27 42 60
5
DRC
VSS7 VSS8 VSS9
CSTOTN
LCAS2
UCAS1
LCAS1
UCAS2
RAS1
CSRM
RAS2
CS1
CS2
AO7
AO6
AO5
AO4
AO3
AO2
AO1
AO8
AO9
WE
OE
UDSN
LDSN
RWN
DTACKN
MODE1
MODE2
MODE3
AI15
CLK
AI16
AI17
AI18
AI19
AI13
AI20
AI21
AI22
AI23
RESETN
AI14
ASN
AI10
AI9
AI8
AI7
AI6
AI5
AI4
AI3
AI2
AI1
AI11
AI12
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6
VDD3 VDD5
REFR
VDD1 VDD2
DRAM
I/F
HOST
I/F
GEN
CS
MUX
REFRESH
A/V MUX Board
IC7503
TDA1305T: Bitstream continuous calibration DAC
Function Overview
The TDA1305T is a dual CMOS DAC with upsampling filter and noise
shaper. The combination of high oversampling up to 16-fold, 2nd order
noise shaping and continuous calibration conversion ensures that only
simple 1st order analog post-filtering is required.
Two on board operational amplifiers convert the digital-to analog
current to an output voltage. Externally connected capacitors perform
the required 1st order filtering so that no further post-filtering is
required.
TDA1305T
7503
21
4
16 7 8
6
17 18 20
23
24
19 13 12
3
11
1 10 28 14
22
25
26
2 9 27 15
5
VSSO VDDO VDDA
OUTPUT
OUTPUT
STAGE
STAGE
RIGHT
LEFT
VSSA
BCK
DATA
+
-
+
-
FILTCR
FILTCL
TEST1
WS
TEST2
VOR
VOL
VDDD
SERIAL
INPUT
DATA
VSSD
TIMING
VDDX VSSX
DEEM1
DEEM2 MUSB DSMB ATSB VREF
CKSL1 CKSL2
SYSCLK
RES CDEC
DAC
Pin name I/O Function
MODE[3:1] I Mode inputs
CLK I Clock
AI[23:1] I Address input:
AI23-AI19: bank of 512 Kbytes
AI18-AI10: column address
AI10-AI01: row address
ASN I Address strobe
UDSN I Upper Data strobe
LDSN I Lower Data strobe
RWN I Read/write
RESETN I Reset
AO[9:1] I Address output
RAS1, RAS2 O Row Address strobe
UCAS1, UCAS2 O Upper column address strobe
LCAS1, LCAS2 O Lower column address strobe
WE O Write enable
OE O Output enable
DTACKN O Data acknowledge
REFR O Refresh
CS1N O Chip select 1
CS2N O Chip select 2
CSROMN O Chip select ROM
CSTN O Chip select total
GND – Ground
VCC – Power supply
Pin Name I/O Function
1 VDDA - Positive supply voltage (analog part)
2 VSSA - supply ground (analog part)
3 TEST1 I test input (connected to ground)
4 BCK I bit clock input
5 WS I word select input
6 DATA I data input
7 CKSL1 I clock selection 1
8 CKSL2 I clock selection 2
9 VSSD - supply ground (digital part)
10 VDDD - Positive supply voltage (digital part)
11 TEST2 I test input (connected to ground)
12 SYSCLK I system clock
13 RES - not connected
14 VDDX - Positive supply voltage
15 VSSX - supply ground
16 CDEC O system clock output
17 DEEM1 I deemphasis on/off
18 DEEM2 I deemphasis on/off
19 MUSB I muting (active low)
20 DSMB I double speed mode
21 ATSB I 12 dB attenuation
22 VOL O left channel output
23 FILTCL I capacitor for left channel 1st order filter
24 FILTCR I capacitor for right channel 1st order filter
25 VOR O right channel output
26 VREF O internal reference voltage for output channels (VDD/2)
27 VSSO - supply ground (operational amplifier)
28 VDDO - positive supply voltage (operational amplifier)