Platinenabbildungen und Schaltpläne / Layout of PCBs and Circuit Diagrams
GDV 100 D
Platinenabbildungen und Schaltpläne / Layout of PCBs and Circuit Diagrams
GDV 100 D
4 - 5
GRUNDIG Service
4 - 6
GRUNDIG Service
Blockschaltplan / Block Circuit Diagram (Digital)
7403-7404
7480-7487
+5VA
4
M27C800
M27C800
uPD424260LE-70
I2C_CLK
CONTROLLER
+5VSTB
27M_LSI
CLKOUT
A[1:19]
A[1:19]
A[1:19]
IRQ_SLAVEN
WAITN
7306
7305
7304
7302
HS
A_CLK
S_ST
S_REQN
S_BS
S_DATA
4
SCKT
WST
2
SCKT
WST
27M_DENC
27M_DSM
SERVICE
0/6/12V
LSI
CONN.
CONN.
CONN.
CONN.
CONN.
RWN
RWN
RESETN
RESETN
HOST PROCESSOR PART
MEMORY PART
AUDIO DECODER/VIDEO ENCODER
MPEG DECODER PART
DSVP PART
TO/FROM
TO/FROM
DVD_B
DVD_G
DVD_R/C
DVD_CVBS
+5V
-5V
RESETN
ACLK
A_CLK
13M5_CLK
4
27M_DENC
7406
PAL_NTSC
DEEM1
DEEM0
SCART1
SCART0
MUTE_EN
SCART_SW
SCART
MUTE_AV
MUTE
1400
I2S AUDIO (2 CHANNEL)
3
7407
SDO0
SCKT
WST
DIG_OUT
RES_DSP
DSP56011
BT865A
DSP
HS
A_DATA
A_WCLK
A_BCLK
A_CSZ
YUV_DVP[0:7]
VS_DVP
RWN
DSACK1N
DSN2
IRQ_DSMN
CS_DSMN
IRQ_DVPN
CS_DVPN
RESETN
A[1:20]
D[0:15]
27M_FIFO
27M_LSI
7303
BA[0:8]
BD[0:63]
YUV_MPEG[0:7]
HS
VS_MPEG
RES_LSIN
RWN
DSN2
CS_LSIN
DSACK1N
IRQ_LSIN
V_VVAL
V_DATA
V_SCLK
V_REQN
A[1:3]
D[8:15]
VIDEO
ENCODER
(DENC)
MPEG AVG DECODER
4MB DRAM
YUV
YUV
CONTROL BUS
ADDRESS BUS
DATA BUS
I2C BUS
CONTROL BUS
ADDRESS BUS
DATA BUS
RESET
27 MHz
32.768 kHz
27M_FIFO
13M5_CLK
27M_CLK
3M68_CLK
40M_CLK
ACLK
4
5
CLOCK
HOST
EPLD
I2C-BUS
EEPROM
DRAM CONTROLLER
DRAM
DRAM
FLASH
FLASH
EPROM
EPROM
2
2
27M_CLK
40M_CLK
SYNTHESIZER
3M68_CLK
+5VA
+5V
-5V
+12V
STB_CONT
POWER
SUPPLY
SERIAL
INTERFACE
ENGINE
BASIC
A/V-MUX
BOARD
DISPLAY
TO/FROM
1200
1101
1201
6
I2S
7112
RESETN
RES_BEN
+5V
+12V
90K_CLK
CLK1M
90K_CLK
CLK1M
27M_DSM
4
S2B
S2B_TXD
S2B_RXD
S2B_SUR
S2B_CPR
4
RX1P
TX1P
CTS1P
RTSEX
D[0:15]
A[0:23]
ASN
DSN
RWN
SIZ[0:1]
DSACK[0:1]N
PAL_NTSC
SWAP
CS[0:2]N
IRQ_LSIN
IRQ_DVPN
IRQ_DSMN
IRQ_SLAVEN
IRQ_I2CN
RES_BEN
RES_DSP
RES_LSIN
DEEM[0:1]
MUTE_EN
SEL_ACLK
PROCESSOR
MC68340PV
7111
7109
MK2742
SDA
SCL
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
2
2
PCF8584
7101
7110
7108
M24C32
A0
A0
A[18:21]
D[8:15]
6M75_CLK
RESETN
CS_I2CN
RWN
DTACK_I2CN
IRQ_I2CN
ASN DSN
SIZ0
CS[0:2]
RESETN
RESET_PLS
ASCOMPN
LDS_DRCN
UDS_DRCN
ASCOMPN
LDS_DRCN
UDS_DRCN
RESETN
RWN
DTACK_DRCN
A[1:23]
AO[1:9]D
7102
7103
7100
7104
7105
7107
7106
RNW
RNW
RNW
RNW
FLASH_CE0N
FLASH_CE1N
EPROM_CE0N
EPROM_CE1N
AO[1:9]D
AO[1:9]D
RAS1ND
RAS2ND
UCAS1ND
UCAS2ND
LCAS1ND
LCAS2ND
WEND
OEND
RAS1ND
UCAS1ND
LCAS1ND
WEND
OEND
RAS2ND
UCAS2ND
LCAS2ND
WEND
OEND
DRC
uPD424260LE-70
D[0:15]
D[0:15]
D[0:15]
D[0:15]
D[0:15]
D[0:15]
A[1:19]
29F800
29F800
RWN
CS_[DSMN,DVPN]
SWAP
CS_LSIN
CS_I2CN
5
3
RNW
FLASH_CE1N
FLASH_CE0N
EPROM_CE1N
EPROM_CE0N
STB_CONT
1100
A_DATA
A_WCLK
A_BCLK
A_CSZ
V_VVAL
V_DATA
V_SCLK
V_REQN
D_D[0:15]
D_A[0:8]
4
DSM
DVP
4MB
DRAM
FIFO
3MB
B_V4
B_WCLK
B_DATA
B_BCLK
B_FLAG
B_SYNC
7200
7201
7202
6
D_F[0:11]
F_D[0:11]
ACLK
I2S AUDIO (5 CHANNEL)
SERIAL VIDEO
YUV_MPEG[0:7]
HS
VS_MPEG
YUV_DVP[0:7]
VS_DVP
SCART[0:1]
4MB
4MB
8MB
8MB
8MB
8MB
uPD424260LE-70
TMS4C2972
DIG_OUT
VIDEO OUT
4MB DRAM
4MB DRAM
4MB DRAM
HAS1179
7939
MCA
P 4-25
P 4-28
P 4-31
P 4-22
P 4-33
P 4-10
P 4-14
P 4-16