GE
RAFT
V
OLUSON
™ P8/V
OLUSON
™P6
DIRECTION 5775469, R
EVISION
3
DRAFT (J
ULY
19, 2018)
B
ASIC
S
ERVICE
M
ANUAL
5-12
Section 5-2 - General Information
5-2-3
Data Flow Control Description
This section describes the functions of the boards vs. different operation modes.
•
DBM64G - Beamformer Motherboard
•
DRFG - Mid-Processor, System Control and DMA Controlle
5-2-3-1
B-Mode
1.) DRFG
The DRFG contains the Clock-Management and PRF-Generator.
It generates(drives) BF (=Beamformer)-FPGA-Clock (200MHz) and Shot-Trigger for the
Beamformer board (DBM64G).
Configures DPI (Dachstein Probe Interface board) and Beamformer (DBM64G with Tx-Frequency,
Tx-Focus, Rx-Focus, LineNo (lateral Position), Tx- Apodization, RX-Apodization, Multibeam, etc.
The DRFG board also contains the Tx-Power-Reference-DAC.
Furthermore it contains Multibeam-DeInterleave, Subtraction Filter (for HI-Mode, see:
3-1-1 "Special B-Mode Techniques" on page 5-13
, DigitalTGC, DC-Canceler, Mixer (Part of
Demodulator), LowPassFilter, Decimation (Pixel rate Conversion), Magnitude Calculator (Part of
Demodulator), Logarithmic Amplifier, Re-Sample, Edge Enhance (Contrast Enhancement through
differentiation), Frame Filter, Blending (adapting Brightness in order to perfectly combine Nearfield-
Frame with Farfield-Frame in FFC-Mode, see:
Section 5-2-3-1-1 "Special B-Mode Techniques" on
.
Multibeam-DeInterleave means: Incoming Pixel order
shot1
pix1
-shot2
pix1
-shot3
pix1
-shot4
pix1
-
shot1
pix2
-shot2
pix2
-shot3
pix2
-shot4
pix2
...
is converted to the new order:
shot1
pix1-
shot1
pix2-
shot1
pix3..... -
shot2
pix1-
shot2
pix2-
shot2
pix3.....
After DC-cancelling the signal is mixed with RX-Frequency and brought to LF-Spectrum, where the
LowPassFilter cuts HF. Mixer and Magnitude-Calculator arrange Complex Demodulation, and
Logarithmic Amplifier arrange the conversion from High-Dynamic LinearSignal to the Low-
Dynamik(e.g.8Bit) Log-Signal. Several Postprocessing steps (LineFilter, FrameFilter, ReSample,
Edge Enhance) enable smooth image quality while keeping contrast high.
a.) Direct Memory Access (DMA) section
B-mode-Data from DRFG is written via Signal Processor (SP) Channel 0 into SDRAM Fifo
Buffer memory. DMA Controller 0 transfers the data into PC main memory where scan
conversion is performed per software.
Cine Mode: Reserved area in PC main memory is used.
2.) DBM64G (Voluson™ P8/Voluson™P6)
This Beamformer board consists of Bemaformer-FPGA, TX-pulser, RX-AFE. DBM64G supports 64
TX/RX channels. Beamformer-FPGA generates TX-Frequency through dividing 200MHz by
2,3,4,5,..., TX-Focus, and Sampling Clocks for the ADC, and manages RX-Foxcus (Delay and
Chain-Adder) and Apodization.
